Yidi Lin has uploaded this change for review.

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WIP: dcm: mt8192: Enable DCM

Enable DCM settings.

/* INFRACFG_AO */
	dcm_infracfg_ao_aximem_bus_dcm(on);
	dcm_infracfg_ao_infra_bus_dcm(on);
	dcm_infracfg_ao_infra_conn_bus_dcm(on);
	dcm_infracfg_ao_infra_rx_p2p_dcm(on);
	dcm_infracfg_ao_peri_bus_dcm(on);
	dcm_infracfg_ao_peri_module_dcm(on);
	/* INFRA_AO_BCRM */
	dcm_infra_ao_bcrm_infra_bus_dcm(on);
	dcm_infra_ao_bcrm_peri_bus_dcm(on);
	/* INFRACFG_AO_MEM */
	/* move to preloader */
	/* dcm_infracfg_ao_mem_dcm_emi_group(on); */

Change-Id: I5528d176b6bb1f9a5960de981766235510e6ebf1
---
M src/soc/mediatek/mt8192/include/soc/pll.h
M src/soc/mediatek/mt8192/pll.c
2 files changed, 76 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/46407/1

diff --git a/src/soc/mediatek/mt8192/include/soc/pll.h b/src/soc/mediatek/mt8192/include/soc/pll.h
index 09c4c471..35e8ff2 100644
--- a/src/soc/mediatek/mt8192/include/soc/pll.h
+++ b/src/soc/mediatek/mt8192/include/soc/pll.h
@@ -306,4 +306,59 @@
 DEFINE_BITFIELD(CLK26CALI_0_TRIGGER, 4, 4)
 DEFINE_BITFIELD(CLK26CALI_1_LOAD_CNT, 25, 16)
 
+enum {
+	INFRACFG_AO_AXIMEM_BUS_DCM_REG0_MASK = ((0x1f << 12) | \
+			(0x1 << 17) | \
+			(0x1 << 18)),
+	INFRACFG_AO_AXIMEM_BUS_DCM_REG0_ON = ((0x10 << 12) | \
+			(0x1 << 17) | \
+			(0x0 << 18)),
+	INFRACFG_AO_INFRA_BUS_DCM_REG0_MASK = ((0x1 << 0) | \
+			(0x1 << 1) | \
+			(0x1 << 3) | \
+			(0x1 << 4) | \
+			(0x1f << 5) | \
+			(0x1f << 10) | \
+			(0x1 << 20) | \
+			(0x1 << 23) | \
+			(0x1 << 30)),
+	INFRACFG_AO_INFRA_BUS_DCM_REG0_ON = ((0x1 << 0) | \
+			(0x1 << 1) | \
+			(0x0 << 3) | \
+			(0x0 << 4) | \
+			(0x10 << 5) | \
+			(0x1 << 10) | \
+			(0x1 << 20) | \
+			(0x1 << 23) | \
+			(0x1 << 30)),
+	INFRACFG_AO_INFRA_CONN_BUS_DCM_REG0_MASK = ((0x1 << 8)),
+	INFRACFG_AO_INFRA_CONN_BUS_DCM_REG0_ON = ((0x1 << 8)),
+	INFRACFG_AO_INFRA_CONN_BUS_DCM_REG1_MASK = ((0x1 << 8)),
+	INFRACFG_AO_INFRA_CONN_BUS_DCM_REG1_ON = ((0x0 << 8)),
+	INFRACFG_AO_INFRA_RX_P2P_DCM_REG0_MASK = ((0xf << 0)),
+	INFRACFG_AO_INFRA_RX_P2P_DCM_REG0_ON = ((0x0 << 0)),
+	INFRACFG_AO_PERI_BUS_DCM_REG0_MASK = ((0x1 << 0) | \
+			(0x1 << 1) | \
+			(0x1 << 3) | \
+			(0x1 << 4) | \
+			(0x1f << 5) | \
+			(0x1f << 10) | \
+			(0x1f << 15) | \
+			(0x1 << 20) | \
+			(0x1 << 21)),
+	INFRACFG_AO_PERI_BUS_DCM_REG0_ON = ((0x1 << 0) | \
+			(0x1 << 1) | \
+			(0x0 << 3) | \
+			(0x0 << 4) | \
+			(0x1f << 5) | \
+			(0x0 << 10) | \
+			(0x1f << 15) | \
+			(0x1 << 20) | \
+			(0x1 << 21)),
+	INFRACFG_AO_PERI_MODULE_DCM_REG0_MASK = ((0x1 << 29) | \
+			(0x1 << 31)),
+	INFRACFG_AO_PERI_MODULE_DCM_REG0_ON = ((0x1 << 29) | \
+			(0x1 << 31)),
+};
+
 #endif /* SOC_MEDIATEK_MT8192_PLL_H */
diff --git a/src/soc/mediatek/mt8192/pll.c b/src/soc/mediatek/mt8192/pll.c
index 24cfafd..0366cd6 100644
--- a/src/soc/mediatek/mt8192/pll.c
+++ b/src/soc/mediatek/mt8192/pll.c
@@ -427,6 +427,27 @@
 	/* enable infrasys DCM */
 	setbits32(&mt8192_infracfg->infra_bus_dcm_ctrl, 0x3 << 21);
 
+	// dcm_infracfg_ao_aximem_bus_dcm
+	clrsetbits_le32(&mt8192_infracfg->infra_aximem_idle_bit_en_0,
+		INFRACFG_AO_AXIMEM_BUS_DCM_REG0_MASK, INFRACFG_AO_AXIMEM_BUS_DCM_REG0_ON);
+	// dcm_infracfg_ao_infra_bus_dcm
+	clrsetbits_le32(&mt8192_infracfg->infra_bus_dcm_ctrl,
+		INFRACFG_AO_INFRA_BUS_DCM_REG0_MASK, INFRACFG_AO_INFRA_BUS_DCM_REG0_ON);
+	// dcm_infracfg_ao_infra_conn_bus_dcm
+	clrsetbits_le32(&mt8192_infracfg->module_sw_cg_2_set,
+		INFRACFG_AO_INFRA_CONN_BUS_DCM_REG0_MASK, INFRACFG_AO_INFRA_CONN_BUS_DCM_REG0_ON);
+	clrsetbits_le32(&mt8192_infracfg->module_sw_cg_2_clr,
+		INFRACFG_AO_INFRA_CONN_BUS_DCM_REG1_MASK, INFRACFG_AO_INFRA_CONN_BUS_DCM_REG1_ON);
+	// dcm_infracfg_ao_infra_rx_p2p_dcm
+	clrsetbits_le32(&mt8192_infracfg->p2p_rx_clk_on,
+		INFRACFG_AO_INFRA_RX_P2P_DCM_REG0_MASK, INFRACFG_AO_INFRA_RX_P2P_DCM_REG0_ON);
+	// dcm_infracfg_ao_peri_bus_dcm
+	clrsetbits_le32(&mt8192_infracfg->peri_bus_dcm_ctrl,
+		INFRACFG_AO_PERI_BUS_DCM_REG0_MASK, INFRACFG_AO_PERI_BUS_DCM_REG0_ON);
+	// dcm_infracfg_ao_peri_module_dcm
+	clrsetbits_le32(&mt8192_infracfg->peri_bus_dcm_ctrl,
+		INFRACFG_AO_PERI_MODULE_DCM_REG0_MASK, INFRACFG_AO_PERI_MODULE_DCM_REG0_ON);
+
 	/* initialize SPM request */
 	setbits32(&mtk_topckgen->clk_scp_cfg_0, 0x3ff);
 	clrsetbits32(&mtk_topckgen->clk_scp_cfg_1, 0x100c, 0x3);

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