Angel Pons has uploaded this change for review.

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mb/**/dsdt.asl: Remove outdated sleepstates.asl comment

Previously, each Intel chipset had its own sleepstates.asl file.
However, this is no longer the case, so drop these comments.

This follows commit 408d1dac9e23250c0e485bbf934771f769b717c1.

Change-Id: I0c0f4ad8bf743010ebdd2d53fcf297aeab64a662
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
---
M src/mainboard/google/dedede/dsdt.asl
M src/mainboard/google/volteer/dsdt.asl
M src/mainboard/intel/jasperlake_rvp/dsdt.asl
M src/mainboard/intel/tglrvp/dsdt.asl
4 files changed, 0 insertions(+), 4 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/39176/1
diff --git a/src/mainboard/google/dedede/dsdt.asl b/src/mainboard/google/dedede/dsdt.asl
index 4134b03..45a1486 100644
--- a/src/mainboard/google/dedede/dsdt.asl
+++ b/src/mainboard/google/dedede/dsdt.asl
@@ -38,7 +38,6 @@
/* Chrome OS specific */
#include <vendorcode/google/chromeos/acpi/chromeos.asl>

- /* Chipset specific sleep states */
#include <southbridge/intel/common/acpi/sleepstates.asl>

/* Chrome OS Embedded Controller */
diff --git a/src/mainboard/google/volteer/dsdt.asl b/src/mainboard/google/volteer/dsdt.asl
index e4bbe90..f62780b 100644
--- a/src/mainboard/google/volteer/dsdt.asl
+++ b/src/mainboard/google/volteer/dsdt.asl
@@ -47,6 +47,5 @@
#include <ec/google/chromeec/acpi/ec.asl>
}

- // Chipset specific sleep states
#include <southbridge/intel/common/acpi/sleepstates.asl>
}
diff --git a/src/mainboard/intel/jasperlake_rvp/dsdt.asl b/src/mainboard/intel/jasperlake_rvp/dsdt.asl
index 8788a1f..4b9a696 100644
--- a/src/mainboard/intel/jasperlake_rvp/dsdt.asl
+++ b/src/mainboard/intel/jasperlake_rvp/dsdt.asl
@@ -58,7 +58,6 @@
}
#endif

- /* Chipset specific sleep states */
#include <southbridge/intel/common/acpi/sleepstates.asl>

/* Mainboard specific */
diff --git a/src/mainboard/intel/tglrvp/dsdt.asl b/src/mainboard/intel/tglrvp/dsdt.asl
index a17f597..8236ccb 100644
--- a/src/mainboard/intel/tglrvp/dsdt.asl
+++ b/src/mainboard/intel/tglrvp/dsdt.asl
@@ -58,7 +58,6 @@
}
#endif

- /* Chipset specific sleep states */
#include <southbridge/intel/common/acpi/sleepstates.asl>

/* Mainboard specific */

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I0c0f4ad8bf743010ebdd2d53fcf297aeab64a662
Gerrit-Change-Number: 39176
Gerrit-PatchSet: 1
Gerrit-Owner: Angel Pons <th3fanbus@gmail.com>
Gerrit-MessageType: newchange