Subrata Banik submitted this change.

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Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Angel Pons: Looks good to me, but someone else must approve Sridhar Siricilla: Looks good to me, but someone else must approve
soc/intel/common/block/sata: Add common SATA driver

Enable PCI_COMMAND_MASTER for SATA controller to ensure device can
behave as a bus master. Otherwise, the device can not generate PCI
accesses.

BUG=b:154900210
TEST=Able to build and boot CML and TGL platform.

Change-Id: Icc6653c26900354df4ee6e5882c60cbe23a5685c
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44299
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
A src/soc/intel/common/block/sata/Kconfig
A src/soc/intel/common/block/sata/Makefile.inc
A src/soc/intel/common/block/sata/sata.c
M src/soc/intel/common/pch/Kconfig
4 files changed, 81 insertions(+), 0 deletions(-)

diff --git a/src/soc/intel/common/block/sata/Kconfig b/src/soc/intel/common/block/sata/Kconfig
new file mode 100644
index 0000000..c7253ae
--- /dev/null
+++ b/src/soc/intel/common/block/sata/Kconfig
@@ -0,0 +1,4 @@
+config SOC_INTEL_COMMON_BLOCK_SATA
+ bool
+ help
+ Common SATA module for Intel PCH
diff --git a/src/soc/intel/common/block/sata/Makefile.inc b/src/soc/intel/common/block/sata/Makefile.inc
new file mode 100644
index 0000000..623d151
--- /dev/null
+++ b/src/soc/intel/common/block/sata/Makefile.inc
@@ -0,0 +1 @@
+ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SATA) += sata.c
diff --git a/src/soc/intel/common/block/sata/sata.c b/src/soc/intel/common/block/sata/sata.c
new file mode 100644
index 0000000..1889700
--- /dev/null
+++ b/src/soc/intel/common/block/sata/sata.c
@@ -0,0 +1,75 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+
+static void sata_final(struct device *dev)
+{
+ /* Set Bus Master */
+ pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
+}
+
+static struct device_operations sata_ops = {
+ .read_resources = pci_dev_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_dev_enable_resources,
+ .final = sata_final,
+ .ops_pci = &pci_dev_ops_pci,
+};
+
+static const unsigned short pci_device_ids[] = {
+ PCI_DEVICE_ID_INTEL_SPT_U_SATA,
+ PCI_DEVICE_ID_INTEL_SPT_U_Y_PREMIUM_SATA,
+ PCI_DEVICE_ID_INTEL_SPT_KBL_SATA,
+ PCI_DEVICE_ID_INTEL_LWB_SATA_AHCI,
+ PCI_DEVICE_ID_INTEL_LWB_SSATA_AHCI,
+ PCI_DEVICE_ID_INTEL_LWB_SATA_RAID,
+ PCI_DEVICE_ID_INTEL_LWB_SSATA_RAID,
+ PCI_DEVICE_ID_INTEL_LWB_SATA_AHCI_SUPER,
+ PCI_DEVICE_ID_INTEL_LWB_SSATA_AHCI_SUPER,
+ PCI_DEVICE_ID_INTEL_LWB_SATA_RAID_SUPER,
+ PCI_DEVICE_ID_INTEL_LWB_SSATA_RAID_SUPER,
+ PCI_DEVICE_ID_INTEL_LWB_SATA_ALT,
+ PCI_DEVICE_ID_INTEL_LWB_SATA_ALT_RST,
+ PCI_DEVICE_ID_INTEL_LWB_SSATA_ALT,
+ PCI_DEVICE_ID_INTEL_LWB_SSATA_ALT_RST,
+ PCI_DEVICE_ID_INTEL_CNL_SATA,
+ PCI_DEVICE_ID_INTEL_CNL_PREMIUM_SATA,
+ PCI_DEVICE_ID_INTEL_CNP_CMP_COMPAT_SATA,
+ PCI_DEVICE_ID_INTEL_CNP_H_SATA,
+ PCI_DEVICE_ID_INTEL_CNP_LP_SATA,
+ PCI_DEVICE_ID_INTEL_ICP_U_SATA,
+ PCI_DEVICE_ID_INTEL_CMP_SATA,
+ PCI_DEVICE_ID_INTEL_CMP_PREMIUM_SATA,
+ PCI_DEVICE_ID_INTEL_CMP_LP_SATA,
+ PCI_DEVICE_ID_INTEL_CMP_H_SATA,
+ PCI_DEVICE_ID_INTEL_CMP_H_HALO_SATA,
+ PCI_DEVICE_ID_INTEL_CMP_H_PREMIUM_SATA,
+ PCI_DEVICE_ID_INTEL_TGP_LP_SATA,
+ PCI_DEVICE_ID_INTEL_TGP_SATA,
+ PCI_DEVICE_ID_INTEL_TGP_PREMIUM_SATA,
+ PCI_DEVICE_ID_INTEL_TGP_COMPAT_SATA,
+ PCI_DEVICE_ID_INTEL_MCC_AHCI_SATA,
+ PCI_DEVICE_ID_INTEL_JSP_SATA_1,
+ PCI_DEVICE_ID_INTEL_JSP_SATA_2,
+ PCI_DEVICE_ID_INTEL_ADP_P_SATA_1,
+ PCI_DEVICE_ID_INTEL_ADP_P_SATA_2,
+ PCI_DEVICE_ID_INTEL_ADP_P_SATA_3,
+ PCI_DEVICE_ID_INTEL_ADP_P_SATA_4,
+ PCI_DEVICE_ID_INTEL_ADP_P_SATA_5,
+ PCI_DEVICE_ID_INTEL_ADP_P_SATA_6,
+ PCI_DEVICE_ID_INTEL_ADP_S_SATA_1,
+ PCI_DEVICE_ID_INTEL_ADP_S_SATA_2,
+ PCI_DEVICE_ID_INTEL_ADP_S_SATA_3,
+ PCI_DEVICE_ID_INTEL_ADP_S_SATA_4,
+ PCI_DEVICE_ID_INTEL_ADP_S_SATA_5,
+ PCI_DEVICE_ID_INTEL_ADP_S_SATA_6,
+ 0
+};
+
+static const struct pci_driver pch_sata __pci_driver = {
+ .ops = &sata_ops,
+ .vendor = PCI_VENDOR_ID_INTEL,
+ .devices = pci_device_ids,
+};
diff --git a/src/soc/intel/common/pch/Kconfig b/src/soc/intel/common/pch/Kconfig
index 6e7f2f6..cca65d6 100644
--- a/src/soc/intel/common/pch/Kconfig
+++ b/src/soc/intel/common/pch/Kconfig
@@ -32,6 +32,7 @@
select SOC_INTEL_COMMON_BLOCK_PCR
select SOC_INTEL_COMMON_BLOCK_PMC
select SOC_INTEL_COMMON_BLOCK_RTC
+ select SOC_INTEL_COMMON_BLOCK_SATA
select SOC_INTEL_COMMON_BLOCK_SMBUS
select SOC_INTEL_COMMON_BLOCK_SPI
select SOC_INTEL_COMMON_BLOCK_TCO

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Icc6653c26900354df4ee6e5882c60cbe23a5685c
Gerrit-Change-Number: 44299
Gerrit-PatchSet: 8
Gerrit-Owner: Subrata Banik <subrata.banik@intel.com>
Gerrit-Reviewer: Angel Pons <th3fanbus@gmail.com>
Gerrit-Reviewer: Furquan Shaikh <furquan@google.com>
Gerrit-Reviewer: Martin Roth <martinroth@google.com>
Gerrit-Reviewer: Patrick Georgi <pgeorgi@google.com>
Gerrit-Reviewer: Patrick Rudolph <siro@das-labor.org>
Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla@intel.com>
Gerrit-Reviewer: Subrata Banik <subrata.banik@intel.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org>
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Gerrit-CC: Andrew McRae <amcrae@google.com>
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