The code in device.c seems to attempt to avoid VGA IO and "legacy" PCI IO windows when allocating (dynamic) resources. I am not convinced that code always works, and those windows would appear to be unnecessary for platforms where we can have programming of CTL_VGA=1, CTL_VGA16=1 and CTL_(NO)_ISA=0 for PCI_BRIDGE_CONTROL.

Sounds plausible, more plausible than the comments in the existing code :)

I think we could first throw errors if assigned resources overlap some of those aliased (and enabled) IO address ranges. Should be easy to (manually) adjust the conflicting static resources when they appear.

How would you implement that? It would be nice to just add the resources
when deciding to set CTL_VGA, but I assume then we'd have to exclude them
from being included in the bridge's regular i/o / memory base regions?

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Id7a07f069dd54331df79f605c6bcda37882a602d
Gerrit-Change-Number: 35516
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Gerrit-Owner: Nico Huber <>
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Gerrit-Reviewer: Michael Niewöhner
Gerrit-Reviewer: Nico Huber <>
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