Tim Wawrzynczak submitted this change.
mb/intel/tglrvp: Add interrupt _CRS under CREC scope
Interrupt _CRS is missing under CREC scope. TGLRVP U/Y has GPP_A15
assigned to MECC_HPD2 as EC_SYNC_IRQ. Configure this GPP_A15 GPIO as
active low and level interruptible for EC sync interrupt configuration.
BUG=None
TEST=Booted to kernel and verified EC_SYNC_IRQ in the scope of CREC
current resource settings.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: Idfe4d4e800866805ee8d758028ac7ddf4b259faa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44103
Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
M src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/ec.h
M src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/gpio.h
M src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c
M src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c
4 files changed, 11 insertions(+), 0 deletions(-)
diff --git a/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/ec.h b/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/ec.h
index c018299..4303faf 100644
--- a/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/ec.h
+++ b/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/ec.h
@@ -56,6 +56,9 @@
/* Enable EC backed ALS device in ACPI */
#define EC_ENABLE_ALS_DEVICE
+/* Enable EC sync interrupt, EC_SYNC_IRQ is defined in baseboard/gpio.h */
+#define EC_ENABLE_SYNC_IRQ
+
/* Enable EC backed PD MCU device in ACPI */
#define EC_ENABLE_PD_MCU_DEVICE
diff --git a/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/gpio.h
index de0adf6..b61276c 100644
--- a/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/gpio.h
+++ b/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/gpio.h
@@ -12,4 +12,7 @@
/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */
#define GPE_EC_WAKE GPE0_LAN_WAK
+/* EC sync IRQ */
+#define EC_SYNC_IRQ GPP_A15_IRQ
+
#endif /* __BASEBOARD_GPIO_H__ */
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c
index 4457506..398a185 100644
--- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c
@@ -54,6 +54,9 @@
/* CNVi */
PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), /* CNV_RF_RST_L */
PAD_CFG_NF(GPP_F5, NONE, DEEP, NF3), /* CNV_CLKREQ0 */
+
+ /* EC_SYNC_IRQ */
+ PAD_CFG_GPI_APIC(GPP_A15, NONE, PLTRST, LEVEL, INVERT), /* MECC_HPD2 */
};
/* Early pad configuration in bootblock */
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c
index 679933a..6c94a1c 100644
--- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c
@@ -51,6 +51,8 @@
PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), /* I2S_MCLK1 */
PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), /* I2S_MCLK2 */
+ /* EC_SYNC_IRQ */
+ PAD_CFG_GPI_APIC(GPP_A15, NONE, PLTRST, LEVEL, INVERT), /* MECC_HPD2 */
};
/* Early pad configuration in bootblock */
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