Attention is currently required from: Federico Amedeo Izzo.
10 comments:
Patchset:
Hi, and thanks for contributing!
File src/mainboard/aoostar/wtr_r1/bootblock.c:
Remove blank line
File src/mainboard/aoostar/wtr_r1/devicetree.cb:
register "usb2_ports[0]" = "USB2_PORT_MID(OC3)" # Type-C Port1
register "usb2_ports[1]" = "USB2_PORT_MID(OC3)" # Type-C Port2
register "usb2_ports[2]" = "USB2_PORT_MID(OC3)" # FPS connector
register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN
register "usb2_ports[4]" = "USB2_PORT_MID(OC3)" # USB3/2 Type A port1
register "usb2_ports[5]" = "USB2_PORT_MID(OC1)" # USB3/2 Type A port2
register "usb2_ports[6]" = "USB2_PORT_MID(OC1)" # USB3/2 Type A port3
register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Type A/ M.2 WLAN
register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC3)" # USB3/2 Type A port1
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # USB3/2 Type A port2
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # USB3/2 Type A port3
r
Please move into the devicetree below.
Patch Set #2, Line 81: device ref ipu off end
Already disabled in chipset devicetree, remove.
Patch Set #2, Line 117: device ref heci1 on end
Enabled in chipset devicetree, remove.
Patch Set #2, Line 230: device ref p2sb on end
P2SB is hidden by the FSP, which is configured accordingly in chipset devicetree. Remove.
Patch Set #2, Line 231: device ref emmc off end
Already disabled in chipset devicetree, remove.
Patch Set #2, Line 233: device ref ufs off end
Already disabled in chipset devicetree, remove.
File src/mainboard/aoostar/wtr_r1/gpio.h:
Remove comments to GPIOs which are configured with PAD_NC.
Patch Set #2, Line 222: /* ------- GPIO Group PCIe vGPIO ------- */
Remove the superfluous comments below.
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