Hung-Te Lin submitted this change.
soc/mediatek/mt8192: Move flash_controller.c to common/
The flash controller driver can be shared among mt8173 and mt819x.
TEST=boot to kernel on Asurada
boot to kernel on Hana (w/o BL31)
Change-Id: I4e5213563189336496122a0f2d8077b3e5245314
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48972
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
---
R src/soc/mediatek/common/flash_controller.c
R src/soc/mediatek/common/include/soc/flash_controller_common.h
M src/soc/mediatek/mt8173/Makefile.inc
D src/soc/mediatek/mt8173/flash_controller.c
D src/soc/mediatek/mt8173/include/soc/flash_controller.h
M src/soc/mediatek/mt8173/include/soc/symbols.h
M src/soc/mediatek/mt8173/spi.c
M src/soc/mediatek/mt8192/Kconfig
M src/soc/mediatek/mt8192/Makefile.inc
M src/soc/mediatek/mt8192/spi.c
10 files changed, 66 insertions(+), 360 deletions(-)
diff --git a/src/soc/mediatek/mt8192/flash_controller.c b/src/soc/mediatek/common/flash_controller.c
similarity index 66%
rename from src/soc/mediatek/mt8192/flash_controller.c
rename to src/soc/mediatek/common/flash_controller.c
index aa43af6..cdda056 100644
--- a/src/soc/mediatek/mt8192/flash_controller.c
+++ b/src/soc/mediatek/common/flash_controller.c
@@ -3,7 +3,8 @@
#include <assert.h>
#include <console/console.h>
#include <device/mmio.h>
-#include <soc/flash_controller.h>
+#include <soc/flash_controller_common.h>
+#include <soc/symbols.h>
#include <spi_flash.h>
#include <spi-generic.h>
#include <stdint.h>
@@ -12,6 +13,8 @@
#include <timer.h>
#include <types.h>
+static struct mtk_nor_regs *const mtk_nor = (void *)SFLASH_REG_BASE;
+
#define GET_NTH_BYTE(d, n) ((d >> (8 * n)) & 0xff)
static int polling_cmd(u32 val)
@@ -20,7 +23,7 @@
stopwatch_init_usecs_expire(&sw, SFLASH_POLLINGREG_US);
- while ((read32(&mt8192_nor->cmd) & val) != 0) {
+ while ((read32(&mtk_nor->cmd) & val) != 0) {
if (stopwatch_expired(&sw))
return -1;
}
@@ -28,20 +31,20 @@
return 0;
}
-static int mt8192_nor_execute_cmd(u8 cmdval)
+static int mtk_nor_execute_cmd(u8 cmdval)
{
u8 val = cmdval & ~SFLASH_AUTOINC;
- write8(&mt8192_nor->cmd, cmdval);
+ write8(&mtk_nor->cmd, cmdval);
return polling_cmd(val);
}
static int sflashhw_read_flash_status(u8 *value)
{
- if (mt8192_nor_execute_cmd(SFLASH_READSTATUS))
+ if (mtk_nor_execute_cmd(SFLASH_READSTATUS))
return -1;
- *value = read8(&mt8192_nor->rdsr);
+ *value = read8(&mtk_nor->rdsr);
return 0;
}
@@ -65,9 +68,9 @@
/* set serial flash program address */
static void set_sfpaddr(u32 addr)
{
- write8(&mt8192_nor->radr[2], GET_NTH_BYTE(addr, 2));
- write8(&mt8192_nor->radr[1], GET_NTH_BYTE(addr, 1));
- write8(&mt8192_nor->radr[0], GET_NTH_BYTE(addr, 0));
+ write8(&mtk_nor->radr[2], GET_NTH_BYTE(addr, 2));
+ write8(&mtk_nor->radr[1], GET_NTH_BYTE(addr, 1));
+ write8(&mtk_nor->radr[0], GET_NTH_BYTE(addr, 0));
}
static int sector_erase(int offset)
@@ -75,16 +78,16 @@
if (wait_for_write_done())
return -1;
- write8(&mt8192_nor->prgdata[5], SFLASH_OP_WREN);
- write8(&mt8192_nor->cnt, 8);
- mt8192_nor_execute_cmd(SFLASH_PRG_CMD);
+ write8(&mtk_nor->prgdata[5], SFLASH_OP_WREN);
+ write8(&mtk_nor->cnt, 8);
+ mtk_nor_execute_cmd(SFLASH_PRG_CMD);
- write8(&mt8192_nor->prgdata[5], SECTOR_ERASE_CMD);
- write8(&mt8192_nor->prgdata[4], GET_NTH_BYTE(offset, 2));
- write8(&mt8192_nor->prgdata[3], GET_NTH_BYTE(offset, 1));
- write8(&mt8192_nor->prgdata[2], GET_NTH_BYTE(offset, 0));
- write8(&mt8192_nor->cnt, 32);
- mt8192_nor_execute_cmd(SFLASH_PRG_CMD);
+ write8(&mtk_nor->prgdata[5], SECTOR_ERASE_CMD);
+ write8(&mtk_nor->prgdata[4], GET_NTH_BYTE(offset, 2));
+ write8(&mtk_nor->prgdata[3], GET_NTH_BYTE(offset, 1));
+ write8(&mtk_nor->prgdata[2], GET_NTH_BYTE(offset, 0));
+ write8(&mtk_nor->cnt, 32);
+ mtk_nor_execute_cmd(SFLASH_PRG_CMD);
if (wait_for_write_done())
return -1;
@@ -100,17 +103,17 @@
IS_ALIGNED(len, SFLASH_DMA_ALIGN));
/* do dma reset */
- write32(&mt8192_nor->fdma_ctl, SFLASH_DMA_SW_RESET);
- write32(&mt8192_nor->fdma_ctl, SFLASH_DMA_WDLE_EN);
+ write32(&mtk_nor->fdma_ctl, SFLASH_DMA_SW_RESET);
+ write32(&mtk_nor->fdma_ctl, SFLASH_DMA_WDLE_EN);
/* flash source address and dram dest address */
- write32(&mt8192_nor->fdma_fadr, addr);
- write32(&mt8192_nor->fdma_dadr, dma_buf);
- write32(&mt8192_nor->fdma_end_dadr, (dma_buf + len));
+ write32(&mtk_nor->fdma_fadr, addr);
+ write32(&mtk_nor->fdma_dadr, dma_buf);
+ write32(&mtk_nor->fdma_end_dadr, (dma_buf + len));
/* start dma */
- write32(&mt8192_nor->fdma_ctl, SFLASH_DMA_TRIGGER | SFLASH_DMA_WDLE_EN);
+ write32(&mtk_nor->fdma_ctl, SFLASH_DMA_TRIGGER | SFLASH_DMA_WDLE_EN);
stopwatch_init_usecs_expire(&sw, SFLASH_POLLINGREG_US);
- while ((read32(&mt8192_nor->fdma_ctl) & SFLASH_DMA_TRIGGER) != 0) {
+ while ((read32(&mtk_nor->fdma_ctl) & SFLASH_DMA_TRIGGER) != 0) {
if (stopwatch_expired(&sw)) {
printk(BIOS_WARNING, "dma read timeout!\n");
return -1;
@@ -132,8 +135,18 @@
u32 done, read_len, copy_len;
uint8_t *dest = (uint8_t *)buf;
- setbits8(&mt8192_nor->read_dual, SFLASH_READ_DUAL_EN);
- write8(&mt8192_nor->prgdata[3], SFLASH_1_1_2_READ);
+ /* Refer to CB:13989 for the hardware limitation on mt8173. */
+ if (CONFIG(SOC_MEDIATEK_MT8173)) {
+ if (!ENV_BOOTBLOCK && !ENV_SEPARATE_VERSTAGE) {
+ dma_buf = (uintptr_t)_dram_dma;
+ dma_buf_len = REGION_SIZE(dram_dma);
+ }
+ }
+
+ if (CONFIG(FLASH_DUAL_READ)) {
+ setbits8(&mtk_nor->read_dual, SFLASH_READ_DUAL_EN);
+ write8(&mtk_nor->prgdata[3], SFLASH_1_1_2_READ);
+ }
/* DMA: start [ skip | len | drop ] = total end */
for (done = 0; done < total; dest += copy_len) {
@@ -161,8 +174,8 @@
set_sfpaddr(addr);
while (len) {
- write8(&mt8192_nor->wdata, *buffer);
- if (mt8192_nor_execute_cmd(SFLASH_WR_TRIGGER | SFLASH_AUTOINC))
+ write8(&mtk_nor->wdata, *buffer);
+ if (mtk_nor_execute_cmd(SFLASH_WR_TRIGGER | SFLASH_AUTOINC))
return -1;
if (wait_for_write_done())
@@ -200,7 +213,7 @@
int mtk_spi_flash_probe(const struct spi_slave *spi,
struct spi_flash *flash)
{
- write32(&mt8192_nor->wrprot, SFLASH_COMMAND_ENABLE);
+ write32(&mtk_nor->wrprot, SFLASH_COMMAND_ENABLE);
memcpy(&flash->spi, spi, sizeof(*spi));
flash->sector_size = 0x1000;
diff --git a/src/soc/mediatek/mt8192/include/soc/flash_controller.h b/src/soc/mediatek/common/include/soc/flash_controller_common.h
similarity index 81%
rename from src/soc/mediatek/mt8192/include/soc/flash_controller.h
rename to src/soc/mediatek/common/include/soc/flash_controller_common.h
index 5373a87..2da3805 100644
--- a/src/soc/mediatek/mt8192/include/soc/flash_controller.h
+++ b/src/soc/mediatek/common/include/soc/flash_controller_common.h
@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-#ifndef __SOC_MEDIATEK_MT8192_FLASH_CONTROLLER_H__
-#define __SOC_MEDIATEK_MT8192_FLASH_CONTROLLER_H__
+#ifndef __SOC_MEDIATEK_COMMON_FLASH_CONTROLLER_COMMON_H__
+#define __SOC_MEDIATEK_COMMON_FLASH_CONTROLLER_COMMON_H__
#include <spi-generic.h>
#include <stdint.h>
@@ -36,7 +36,7 @@
};
/* register Offset */
-struct mt8192_nor_regs {
+struct mtk_nor_regs {
u32 cmd;
u32 cnt;
u32 rdsr;
@@ -73,9 +73,8 @@
u32 fdma_dadr;
u32 fdma_end_dadr;
};
-check_member(mt8192_nor_regs, fdma_end_dadr, 0x724);
-static struct mt8192_nor_regs *const mt8192_nor = (void *)SFLASH_REG_BASE;
+check_member(mtk_nor_regs, fdma_end_dadr, 0x724);
int mtk_spi_flash_probe(const struct spi_slave *spi, struct spi_flash *flash);
-#endif /* __SOC_MEDIATEK_MT8192_FLASH_CONTROLLER_H__ */
+#endif /* __SOC_MEDIATEK_COMMON_FLASH_CONTROLLER_COMMON_H__ */
diff --git a/src/soc/mediatek/mt8173/Makefile.inc b/src/soc/mediatek/mt8173/Makefile.inc
index 871a689..e824e54 100644
--- a/src/soc/mediatek/mt8173/Makefile.inc
+++ b/src/soc/mediatek/mt8173/Makefile.inc
@@ -3,7 +3,7 @@
ifeq ($(CONFIG_SOC_MEDIATEK_MT8173),y)
bootblock-y += bootblock.c
-bootblock-$(CONFIG_SPI_FLASH) += flash_controller.c
+bootblock-$(CONFIG_SPI_FLASH) += ../common/flash_controller.c
bootblock-y += ../common/i2c.c i2c.c
bootblock-y += ../common/pll.c pll.c
bootblock-y += ../common/spi.c spi.c
@@ -27,12 +27,12 @@
verstage-y += ../common/timer.c
verstage-y += timer.c
verstage-y += ../common/wdt.c ../common/reset.c
-verstage-$(CONFIG_SPI_FLASH) += flash_controller.c
+verstage-$(CONFIG_SPI_FLASH) += ../common/flash_controller.c
verstage-y += ../common/gpio.c gpio.c
################################################################################
-romstage-$(CONFIG_SPI_FLASH) += flash_controller.c
+romstage-$(CONFIG_SPI_FLASH) += ../common/flash_controller.c
romstage-y += ../common/pll.c pll.c
romstage-y += ../common/timer.c
romstage-y += timer.c
@@ -53,7 +53,7 @@
ramstage-y += emi.c
ramstage-y += ../common/spi.c spi.c
-ramstage-$(CONFIG_SPI_FLASH) += flash_controller.c
+ramstage-$(CONFIG_SPI_FLASH) += ../common/flash_controller.c
ramstage-y += soc.c ../common/mtcmos.c
ramstage-y += ../common/timer.c
ramstage-y += timer.c
diff --git a/src/soc/mediatek/mt8173/flash_controller.c b/src/soc/mediatek/mt8173/flash_controller.c
deleted file mode 100644
index 64eff2e..0000000
--- a/src/soc/mediatek/mt8173/flash_controller.c
+++ /dev/null
@@ -1,236 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* NOR Flash is clocked with 26MHz, from CLK26M -> TOP_SPINFI_IFR */
-
-#include <device/mmio.h>
-#include <assert.h>
-#include <console/console.h>
-#include <spi_flash.h>
-#include <spi-generic.h>
-#include <string.h>
-#include <symbols.h>
-#include <timer.h>
-#include <soc/symbols.h>
-#include <soc/flash_controller.h>
-#include <types.h>
-
-#define get_nth_byte(d, n) ((d >> (8 * n)) & 0xff)
-
-static int polling_cmd(u32 val)
-{
- struct stopwatch sw;
-
- stopwatch_init_usecs_expire(&sw, SFLASH_POLLINGREG_US);
-
- while ((read32(&mt8173_nor->cmd) & val) != 0) {
- if (stopwatch_expired(&sw))
- return -1;
- }
-
- return 0;
-}
-
-static int mt8173_nor_execute_cmd(u8 cmdval)
-{
- u8 val = cmdval & ~(SFLASH_AUTOINC);
-
- write8(&mt8173_nor->cmd, cmdval);
- return polling_cmd(val);
-}
-
-static int sflashhw_read_flash_status(u8 *value)
-{
- if (mt8173_nor_execute_cmd(SFLASH_READSTATUS))
- return -1;
-
- *value = read8(&mt8173_nor->rdsr);
- return 0;
-}
-
-static int wait_for_write_done(void)
-{
- struct stopwatch sw;
- u8 reg;
-
- stopwatch_init_usecs_expire(&sw, SFLASH_POLLINGREG_US);
-
- while (sflashhw_read_flash_status(®) == 0) {
- if (!(reg & SFLASH_WRITE_IN_PROGRESS))
- return 0;
- if (stopwatch_expired(&sw))
- return -1;
- }
-
- return -1;
-}
-
-/* set serial flash program address */
-static void set_sfpaddr(u32 addr)
-{
- write8(&mt8173_nor->radr[2], get_nth_byte(addr, 2));
- write8(&mt8173_nor->radr[1], get_nth_byte(addr, 1));
- write8(&mt8173_nor->radr[0], get_nth_byte(addr, 0));
-}
-
-static int sector_erase(int offset)
-{
- if (wait_for_write_done())
- return -1;
-
- write8(&mt8173_nor->prgdata[5], SFLASH_OP_WREN);
- write8(&mt8173_nor->cnt, 8);
- mt8173_nor_execute_cmd(SFLASH_PRG_CMD);
-
- write8(&mt8173_nor->prgdata[5], SECTOR_ERASE_CMD);
- write8(&mt8173_nor->prgdata[4], get_nth_byte(offset, 2));
- write8(&mt8173_nor->prgdata[3], get_nth_byte(offset, 1));
- write8(&mt8173_nor->prgdata[2], get_nth_byte(offset, 0));
- write8(&mt8173_nor->cnt, 32);
- mt8173_nor_execute_cmd(SFLASH_PRG_CMD);
-
- if (wait_for_write_done())
- return -1;
-
- return 0;
-}
-
-static int dma_read(u32 addr, u8 *buf, u32 len, uintptr_t dma_buf,
- size_t dma_buf_len)
-{
- struct stopwatch sw;
-
- assert(IS_ALIGNED((uintptr_t)buf, SFLASH_DMA_ALIGN) &&
- IS_ALIGNED(len, SFLASH_DMA_ALIGN) &&
- len <= dma_buf_len);
-
- /* do dma reset */
- write32(&mt8173_nor->fdma_ctl, SFLASH_DMA_SW_RESET);
- write32(&mt8173_nor->fdma_ctl, SFLASH_DMA_WDLE_EN);
- /* flash source address and dram dest address */
- write32(&mt8173_nor->fdma_fadr, addr);
- write32(&mt8173_nor->fdma_dadr, dma_buf);
- write32(&mt8173_nor->fdma_end_dadr, (dma_buf + len));
- /* start dma */
- write32(&mt8173_nor->fdma_ctl, SFLASH_DMA_TRIGGER | SFLASH_DMA_WDLE_EN);
-
- stopwatch_init_usecs_expire(&sw, SFLASH_POLLINGREG_US);
- while ((read32(&mt8173_nor->fdma_ctl) & SFLASH_DMA_TRIGGER) != 0) {
- if (stopwatch_expired(&sw)) {
- printk(BIOS_WARNING, "dma read timeout!\n");
- return -1;
- }
- }
-
- memcpy(buf, (const void *)dma_buf, len);
- return 0;
-}
-
-static int pio_read(u32 addr, u8 *buf, u32 len)
-{
- set_sfpaddr(addr);
- while (len) {
- if (mt8173_nor_execute_cmd(SFLASH_RD_TRIGGER | SFLASH_AUTOINC))
- return -1;
-
- *buf++ = read8(&mt8173_nor->rdata);
- len--;
- }
- return 0;
-}
-
-static int nor_read(const struct spi_flash *flash, u32 addr, size_t len,
- void *buf)
-{
- u32 next;
-
- size_t done = 0;
- uintptr_t dma_buf;
- size_t dma_buf_len;
-
- if (!IS_ALIGNED((uintptr_t)buf, SFLASH_DMA_ALIGN)) {
- next = MIN(ALIGN_UP((uintptr_t)buf, SFLASH_DMA_ALIGN) -
- (uintptr_t)buf, len);
- if (pio_read(addr, buf, next))
- return -1;
- done += next;
- }
-
- if (ENV_BOOTBLOCK || ENV_SEPARATE_VERSTAGE) {
- dma_buf = (uintptr_t)_dma_coherent;
- dma_buf_len = REGION_SIZE(dma_coherent);
- } else {
- dma_buf = (uintptr_t)_dram_dma;
- dma_buf_len = REGION_SIZE(dram_dma);
- }
-
- while (len - done >= SFLASH_DMA_ALIGN) {
- next = MIN(dma_buf_len, ALIGN_DOWN(len - done,
- SFLASH_DMA_ALIGN));
- if (dma_read(addr + done, buf + done, next, dma_buf,
- dma_buf_len))
- return -1;
- done += next;
- }
- next = len - done;
- if (next > 0 && pio_read(addr + done, buf + done, next))
- return -1;
- return 0;
-}
-
-static int nor_write(const struct spi_flash *flash, u32 addr, size_t len,
- const void *buf)
-{
- const u8 *buffer = (const u8 *)buf;
-
- set_sfpaddr(addr);
- while (len) {
- write8(&mt8173_nor->wdata, *buffer);
- if (mt8173_nor_execute_cmd(SFLASH_WR_TRIGGER | SFLASH_AUTOINC))
- return -1;
-
- if (wait_for_write_done())
- return -1;
- buffer++;
- len--;
- }
- return 0;
-}
-
-static int nor_erase(const struct spi_flash *flash, u32 offset, size_t len)
-{
- int sector_start = offset;
- int sector_num = (u32)len / flash->sector_size;
-
- while (sector_num) {
- if (!sector_erase(sector_start)) {
- sector_start += flash->sector_size;
- sector_num--;
- } else {
- printk(BIOS_WARNING, "Erase failed at 0x%x!\n",
- sector_start);
- return -1;
- }
- }
- return 0;
-}
-
-const struct spi_flash_ops spi_flash_ops = {
- .read = nor_read,
- .write = nor_write,
- .erase = nor_erase,
-};
-
-int mtk_spi_flash_probe(const struct spi_slave *spi,
- struct spi_flash *flash)
-{
- write32(&mt8173_nor->wrprot, SFLASH_COMMAND_ENABLE);
- memcpy(&flash->spi, spi, sizeof(*spi));
-
- flash->sector_size = 0x1000;
- flash->erase_cmd = SECTOR_ERASE_CMD;
- flash->size = CONFIG_ROM_SIZE;
-
- flash->ops = &spi_flash_ops;
-
- return 0;
-}
diff --git a/src/soc/mediatek/mt8173/include/soc/flash_controller.h b/src/soc/mediatek/mt8173/include/soc/flash_controller.h
deleted file mode 100644
index 6ac8da3..0000000
--- a/src/soc/mediatek/mt8173/include/soc/flash_controller.h
+++ /dev/null
@@ -1,78 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef __SOC_MEDIATEK_MT8173_FLASH_CONTROLLER_H__
-#define __SOC_MEDIATEK_MT8173_FLASH_CONTROLLER_H__
-
-#include <spi-generic.h>
-#include <stdint.h>
-#include <soc/addressmap.h>
-
-enum {
- SFLASH_POLLINGREG_US = 500000,
- SFLASH_WRBUF_SIZE = 128,
- SFLASHNAME_LENGTH = 16,
- SFLASH_WRITE_IN_PROGRESS = 1,
- SFLASH_COMMAND_ENABLE = 0x30,
- SFLASH_DMA_ALIGN = 0x10,
-
- /* NOR flash controller commands */
- SFLASH_RD_TRIGGER = 1 << 0,
- SFLASH_READSTATUS = 1 << 1,
- SFLASH_PRG_CMD = 1 << 2,
- SFLASH_WR_TRIGGER = 1 << 4,
- SFLASH_WRITESTATUS = 1 << 5,
- SFLASH_AUTOINC = 1 << 7,
- /* NOR flash commands */
- SFLASH_OP_WREN = 0x6,
- SECTOR_ERASE_CMD = 0x20,
- SFLASH_UNPROTECTED = 0x0,
- /* DMA commands */
- SFLASH_DMA_TRIGGER = 1 << 0,
- SFLASH_DMA_SW_RESET = 1 << 1,
- SFLASH_DMA_WDLE_EN = 1 << 2
-};
-
-/* register Offset */
-struct mt8173_nor_regs {
- u32 cmd;
- u32 cnt;
- u32 rdsr;
- u32 rdata;
- u32 radr[3];
- u32 wdata;
- u32 prgdata[6];
- u32 shreg[10];
- u32 cfg[2];
- u32 shreg10;
- u32 status[5];
- u32 timing;
- u32 flash_cfg;
- u32 reserved2[3];
- u32 sf_time;
- u32 reserved3;
- u32 diff_addr;
- u32 del_sel[2];
- u32 intrstus;
- u32 intren;
- u32 pp_ctl;
- u32 cfg3;
- u32 chksum_ctl;
- u32 chksum;
- u32 aaicmd;
- u32 wrprot;
- u32 radr3;
- u32 read_dual;
- u32 delsel[3];
- u32 reserved[397];
- u32 cfg1_bri[2];
- u32 fdma_ctl;
- u32 fdma_fadr;
- u32 fdma_dadr;
- u32 fdma_end_dadr;
-};
-check_member(mt8173_nor_regs, fdma_end_dadr, 0x724);
-static struct mt8173_nor_regs *const mt8173_nor = (void *)SFLASH_REG_BASE;
-
-int mtk_spi_flash_probe(const struct spi_slave *spi, struct spi_flash *flash);
-
-#endif /* __SOC_MEDIATEK_MT8173_FLASH_CONTROLLER_H__ */
diff --git a/src/soc/mediatek/mt8173/include/soc/symbols.h b/src/soc/mediatek/mt8173/include/soc/symbols.h
index 1cf6dde..ae5d998 100644
--- a/src/soc/mediatek/mt8173/include/soc/symbols.h
+++ b/src/soc/mediatek/mt8173/include/soc/symbols.h
@@ -2,6 +2,7 @@
#ifndef __SOC_MEDIATEK_MT8173_DRAM_DMA_H__
#define __SOC_MEDIATEK_MT8173_DRAM_DMA_H__
+#include <symbols.h>
DECLARE_REGION(dram_dma)
diff --git a/src/soc/mediatek/mt8173/spi.c b/src/soc/mediatek/mt8173/spi.c
index dd5c2ae..4abd650 100644
--- a/src/soc/mediatek/mt8173/spi.c
+++ b/src/soc/mediatek/mt8173/spi.c
@@ -4,7 +4,7 @@
#include <assert.h>
#include <spi_flash.h>
#include <soc/addressmap.h>
-#include <soc/flash_controller.h>
+#include <soc/flash_controller_common.h>
#include <soc/gpio.h>
#include <soc/spi.h>
diff --git a/src/soc/mediatek/mt8192/Kconfig b/src/soc/mediatek/mt8192/Kconfig
index 7373fe1..fd0a4cd 100644
--- a/src/soc/mediatek/mt8192/Kconfig
+++ b/src/soc/mediatek/mt8192/Kconfig
@@ -75,4 +75,11 @@
help
The file name of the MediaTek SSPM firmware.
+config FLASH_DUAL_READ
+ bool
+ default y
+ help
+ When this option is enabled, the flash controller provides the ability
+ to dual read mode.
+
endif
diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc
index cb3b6c2..ce94a46 100644
--- a/src/soc/mediatek/mt8192/Makefile.inc
+++ b/src/soc/mediatek/mt8192/Makefile.inc
@@ -3,7 +3,7 @@
bootblock-y += ../common/auxadc.c
bootblock-y += bootblock.c
bootblock-y += eint_event.c
-bootblock-y += flash_controller.c
+bootblock-y += ../common/flash_controller.c
bootblock-y += ../common/gpio.c gpio.c
bootblock-y += ../common/i2c.c i2c.c
bootblock-y += ../common/mmu_operations.c
@@ -18,7 +18,7 @@
bootblock-y += mt6359p.c
verstage-y += ../common/auxadc.c
-verstage-y += flash_controller.c
+verstage-y += ../common/flash_controller.c
verstage-y += ../common/gpio.c gpio.c
verstage-y += ../common/i2c.c i2c.c
verstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c
@@ -30,7 +30,7 @@
romstage-y += dramc_pi_main.c dramc_pi_basic_api.c dramc_pi_calibration_api.c
romstage-y += dramc_utility.c dramc_dvfs.c
romstage-y += emi.c
-romstage-y += flash_controller.c
+romstage-y += ../common/flash_controller.c
romstage-y += ../common/gpio.c gpio.c
romstage-y += ../common/i2c.c i2c.c
romstage-y += ../common/mmu_operations.c mmu_operations.c
@@ -46,7 +46,7 @@
ramstage-y += devapc.c
ramstage-y += dpm.c
ramstage-y += ../common/dsi.c ../common/mtk_mipi_dphy.c
-ramstage-y += flash_controller.c
+ramstage-y += ../common/flash_controller.c
ramstage-y += ../common/gpio.c gpio.c
ramstage-y += ../common/i2c.c i2c.c
ramstage-y += emi.c
diff --git a/src/soc/mediatek/mt8192/spi.c b/src/soc/mediatek/mt8192/spi.c
index d35e5ad..f7a8756 100644
--- a/src/soc/mediatek/mt8192/spi.c
+++ b/src/soc/mediatek/mt8192/spi.c
@@ -3,7 +3,7 @@
#include <device/mmio.h>
#include <assert.h>
#include <soc/addressmap.h>
-#include <soc/flash_controller.h>
+#include <soc/flash_controller_common.h>
#include <soc/gpio.h>
#include <soc/spi.h>
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