Attention is currently required from: Patrick Rudolph.
Tim Wawrzynczak uploaded patch set #5 to this change.
soc/intel/alderlake: Define soc_get_pcie_rp_type
In order to distinguish PCH from CPU PCIe RPs, define the
soc_get_pcie_rp_type function for Alder Lake. While we're
here, add PCIe RP group definitions for PCH-M chipsets.
BUG=b:197983574
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I7438513e10b7cea8dac678b97a901b710247c188
---
M src/soc/intel/alderlake/Makefile.inc
M src/soc/intel/alderlake/cpu.c
M src/soc/intel/alderlake/pcie_rp.c
3 files changed, 62 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/59854/5
To view, visit change 59854. To unsubscribe, or for help writing mail filters, visit settings.