Patch Set 4:

Patch Set 1:

Patch Set 1:

Did you compare testing results between CML-H and other platforms like SKL/KBL-H?

Yes, SHL/KBL H also has total 8 SATA port. The only difference is SPD bit definitions there. thats we have already handled like this

https://github.com/coreboot/coreboot/blob/master/src/soc/intel/common/block/sata/Kconfig#L6

Difference between H and LP would be for SATA, LP has 0-2 implemented and rest 3-7 reserved.

I wonder why I had no problems with this on X11SSM-F (100series PCH-H) so far
May your SATA direct connect Port is between 0-2, else you would also see this issue for sure.

I have 8 SATA Ports and use 2-6 and there are no problems

You seems lucky that in ur case FSP might have already written to SPD register and as this SPD register is RW/O hence coreboot next writes has no effect. But if FSP skips settings those SPD and coreboot only know abut (ports 0-2) and disables other ports it would have result the same what i'm seeing now.

So now question is do you like to over commit that FSP will always things proper and coreboot might not need to program SPD bits at finalize stage ? This code might be like double insurance in coreboot to handle such misses from FSP.

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