Jose Trujillo has uploaded this change for review.
Port of Kontron bSC2 COMe module
Change-Id: I2932af6016b044fa807da00acc7b147ef1c7c45e
Signed-off-by: JTCEA <ce.autom@protonmail.com>
---
A src/mainboard/kontron/bSC2/Kconfig
A src/mainboard/kontron/bSC2/Kconfig.name
A src/mainboard/kontron/bSC2/Makefile.inc
A src/mainboard/kontron/bSC2/acpi/ec.asl
A src/mainboard/kontron/bSC2/acpi/platform.asl
A src/mainboard/kontron/bSC2/acpi/superio.asl
A src/mainboard/kontron/bSC2/acpi_tables.c
A src/mainboard/kontron/bSC2/board_info.txt
A src/mainboard/kontron/bSC2/cmos.default
A src/mainboard/kontron/bSC2/cmos.layout
A src/mainboard/kontron/bSC2/devicetree.cb
A src/mainboard/kontron/bSC2/devicetree.cb.orig
A src/mainboard/kontron/bSC2/dsdt.asl
A src/mainboard/kontron/bSC2/early_init.c
A src/mainboard/kontron/bSC2/gma-mainboard.ads
A src/mainboard/kontron/bSC2/gma-mainboard.ads.orig
A src/mainboard/kontron/bSC2/gpio.c
A src/mainboard/kontron/bSC2/hda_verb.c
A src/mainboard/kontron/bSC2/mainboard.c
19 files changed, 1,259 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/45658/1
diff --git a/src/mainboard/kontron/bSC2/Kconfig b/src/mainboard/kontron/bSC2/Kconfig
new file mode 100644
index 0000000..66a74cd
--- /dev/null
+++ b/src/mainboard/kontron/bSC2/Kconfig
@@ -0,0 +1,61 @@
+if BOARD_KONTRON_bSC2
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+ select BOARD_ROMSIZE_KB_8192
+ select HAVE_ACPI_RESUME
+ select HAVE_ACPI_TABLES
+ select INTEL_INT15
+ select MAINBOARD_HAS_LIBGFXINIT # FIXME: check this
+ select NORTHBRIDGE_INTEL_SANDYBRIDGE
+ select SERIRQ_CONTINUOUS_MODE
+ select SOUTHBRIDGE_INTEL_BD82X6X
+ select USE_NATIVE_RAMINIT
+
+ select HAVE_OPTION_TABLE
+ select HAVE_CMOS_DEFAULT
+ select USE_OPTION_TABLE
+ select SUPERIO_SMSC_SMSCSUPERIO
+ select DRIVERS_PS2_KEYBOARD
+ select GFX_GMA_PANEL_1_ON_LVDS
+ select BOOT_DEVICE_SUPPORTS_WRITES
+ select SMMSTORE
+ # select NO_POST
+
+config MAINBOARD_DIR
+ string
+ default kontron/bSC2
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "COMe-bCS2"
+
+config DRAM_RESET_GATE_GPIO # FIXME: check this
+ int
+ default 60
+
+config MAX_CPUS
+ int
+ default 4
+
+config CBFS_SIZE
+ hex
+ default 0x300000
+
+config INCLUDE_CONFIG_FILE
+ bool
+ default n
+
+config CPU_UCODE_BINARIES
+ string
+ default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/06-2a-07"
+
+config DRIVERS_UART_8250IO
+ bool
+ default y
+
+config CONSOLE_CBMEM
+ bool
+ default n
+
+endif
diff --git a/src/mainboard/kontron/bSC2/Kconfig.name b/src/mainboard/kontron/bSC2/Kconfig.name
new file mode 100644
index 0000000..b0110b6
--- /dev/null
+++ b/src/mainboard/kontron/bSC2/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_KONTRON_bSC2
+ bool "bCS2-COMe"
diff --git a/src/mainboard/kontron/bSC2/Makefile.inc b/src/mainboard/kontron/bSC2/Makefile.inc
new file mode 100644
index 0000000..18391d8
--- /dev/null
+++ b/src/mainboard/kontron/bSC2/Makefile.inc
@@ -0,0 +1,5 @@
+bootblock-y += early_init.c
+bootblock-y += gpio.c
+romstage-y += early_init.c
+romstage-y += gpio.c
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
diff --git a/src/mainboard/kontron/bSC2/acpi/ec.asl b/src/mainboard/kontron/bSC2/acpi/ec.asl
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/src/mainboard/kontron/bSC2/acpi/ec.asl
diff --git a/src/mainboard/kontron/bSC2/acpi/platform.asl b/src/mainboard/kontron/bSC2/acpi/platform.asl
new file mode 100644
index 0000000..afb8abb
--- /dev/null
+++ b/src/mainboard/kontron/bSC2/acpi/platform.asl
@@ -0,0 +1,8 @@
+Method(_WAK, 1)
+{
+ Return(Package() {0, 0})
+}
+
+Method(_PTS, 1)
+{
+}
diff --git a/src/mainboard/kontron/bSC2/acpi/superio.asl b/src/mainboard/kontron/bSC2/acpi/superio.asl
new file mode 100644
index 0000000..8c920eb
--- /dev/null
+++ b/src/mainboard/kontron/bSC2/acpi/superio.asl
@@ -0,0 +1,262 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+// Scope is \_SB.PCI0.LPCB
+
+#define SIO_ENABLE_COM1
+#define SIO_ENABLE_COM2
+#define SIO_ENABLE_PS2K
+#define SIO_ENABLE_PS2M
+#define SIO_ENABLE_COM3
+#define SIO_ENABLE_COM4
+
+Device (SIO) {
+ Name (_ADR, 0x2E)
+ OperationRegion (SIOA, SystemIO, 0x2E, 0x02)
+ Field (SIOA, ByteAcc, NoLock, Preserve)
+ {
+ SI2E, 8,
+ SI2F, 8,
+ }
+
+ IndexField (SI2E, SI2F, ByteAcc, NoLock, Preserve)
+ {
+ Offset (0x02),
+ SCNT, 8, /* Configure Control */
+ Offset (0x07),
+ SLDN, 8, /* Logical Device Number */
+ Offset (0x30),
+ SACT, 8, /* Activate */
+ Offset (0x60),
+ IO0H, 8, /* Base Address 0 MSB */
+ IO0L, 8, /* Base Address 0 LSB */
+ Offset (0x62),
+ IO1H, 8, /* Base Address 1 MSB */
+ IO1L, 8, /* Base Address 1 LSB */
+ Offset (0x70),
+ IQ00, 8, /* Interrupt Select */
+ IQ01, 8,
+ }
+
+ Name (SFDC, 0) /* Floppy Disk */
+ Name (SPPC, 3) /* Parallel Port */
+ Name (SSP1, 4) /* Serial Port 1 */
+ Name (SSP2, 5) /* Serial Port 2 */
+ Name (SKBC, 7) /* Keyboard & Mouse */
+ Name (SRRB, 10) /* Runtime Register Block */
+ Name (SSP3, 11) /* Serial Port 3 */
+ Name (SSP4, 12) /* Serial Port 4 */
+
+ Method (ENTR, 0, NotSerialized)
+ {
+ Store (0x55, SI2E)
+ }
+
+ Method (EXIT, 0, NotSerialized)
+ {
+ Store (0xaa, SI2E)
+ }
+
+ /* Parse activate register for an LDN */
+ Method (ISEN, 1, NotSerialized)
+ {
+ ENTR ()
+ Store (Arg0, SLDN)
+ Store (SACT, Local0)
+ EXIT ()
+
+ /* Check if it exists */
+ If (LEqual (Local0, 0xFF))
+ {
+ Return (0x00)
+ }
+
+ /* Check if activated */
+ If (LEqual (Local0, One))
+ {
+ Return (0x0F)
+ }
+ Else
+ {
+ Return (0x0D)
+ }
+ }
+
+ /* Enable an LDN via the activate register */
+ Method (SENA, 1, NotSerialized)
+ {
+ ENTR ()
+ Store (Arg0, SLDN)
+ Store (One, SACT)
+ EXIT ()
+ }
+
+ /* Disable an LDN via the activate register */
+ Method (SDIS, 1, NotSerialized)
+ {
+ ENTR ()
+ Store (Arg0, SLDN)
+ Store (Zero, SACT)
+ EXIT ()
+ }
+
+#ifdef SIO_ENABLE_COM1
+ Device (COM1) {
+ Name (_HID, EISAID ("PNP0501"))
+ Name (_UID, 1)
+
+ Method (_STA, 0, NotSerialized) {
+ Return (ISEN (SSP1))
+ }
+
+ Name (_CRS, ResourceTemplate ()
+ {
+ IO (Decode16, 0x03F8, 0x03F8, 0x08, 0x08)
+ //IRQNoFlags () {4}
+ IRQ (Edge, ActiveHigh, Exclusive) {4}
+ })
+
+ Name (_PRS, ResourceTemplate ()
+ {
+ IO (Decode16, 0x03F8, 0x03F8, 0x08, 0x08)
+ //IRQNoFlags () {4}
+ IRQ (Edge, ActiveHigh, Exclusive) {4}
+ })
+ }
+#endif
+
+#ifdef SIO_ENABLE_COM2
+ Device (COM2) {
+ Name (_HID, EISAID ("PNP0501"))
+ Name (_UID, 2)
+
+ Method (_STA, 0, NotSerialized) {
+ Return (ISEN (SSP2))
+ }
+
+ Name (_CRS, ResourceTemplate ()
+ {
+ IO (Decode16, 0x02F8, 0x02F8, 0x08, 0x08)
+ //IRQNoFlags () {3}
+ IRQ (Edge, ActiveHigh, Exclusive) {3}
+ })
+
+ Name (_PRS, ResourceTemplate ()
+ {
+ IO (Decode16, 0x02F8, 0x02F8, 0x08, 0x08)
+ //IRQNoFlags () {3}
+ IRQ (Edge, ActiveHigh, Exclusive) {3}
+ })
+ }
+#endif
+
+#ifdef SIO_ENABLE_PS2K
+ Device (PS2K) // Keyboard
+ {
+ Name (_HID, EISAID("PNP0303"))
+ Name (_CID, EISAID("PNP030B"))
+
+ Method (_STA, 0, NotSerialized) {
+ Return (ISEN (SKBC))
+ }
+
+ Name (_CRS, ResourceTemplate()
+ {
+ IO (Decode16, 0x60, 0x60, 0x01, 0x01)
+ IO (Decode16, 0x64, 0x64, 0x01, 0x01)
+ IRQNoFlags () {1}
+ })
+
+ Name (_PRS, ResourceTemplate()
+ {
+ IO (Decode16, 0x60, 0x60, 0x01, 0x01)
+ IO (Decode16, 0x64, 0x64, 0x01, 0x01)
+ IRQNoFlags () {1}
+ })
+ }
+#endif
+
+#ifdef SIO_ENABLE_PS2M
+ Device (PS2M) // Mouse
+ {
+ Name (_HID, EISAID("PNP0F13"))
+
+ Method (_STA, 0, NotSerialized) {
+ Return (ISEN (SKBC))
+ }
+
+ Name (_CRS, ResourceTemplate()
+ {
+ IRQNoFlags () {12}
+ })
+
+ Name (_PRS, ResourceTemplate()
+ {
+ IRQNoFlags () {12}
+ })
+ }
+#endif
+
+#ifdef SIO_ENABLE_COM3
+ Device (COM3) {
+ Name (_HID, EISAID ("PNP0501"))
+ Name (_UID, 3)
+
+ Method (_STA, 0, NotSerialized) {
+ Return (ISEN (SSP3))
+ }
+
+ Name (_CRS, ResourceTemplate ()
+ {
+ IO (Decode16, 0x03E8, 0x03E8, 0x08, 0x08)
+ //IRQNoFlags () {5}
+ IRQ (Edge, ActiveHigh, Exclusive) {5}
+ })
+
+ Name (_PRS, ResourceTemplate ()
+ {
+ IO (Decode16, 0x03E8, 0x03E8, 0x08, 0x08)
+ //IRQNoFlags () {5}
+ IRQ (Edge, ActiveHigh, Exclusive) {5}
+ })
+ }
+#endif
+
+#ifdef SIO_ENABLE_COM4
+ Device (COM4) {
+ Name (_HID, EISAID ("PNP0501"))
+ Name (_UID, 4)
+
+ Method (_STA, 0, NotSerialized) {
+ Return (ISEN (SSP4))
+ }
+
+ Name (_CRS, ResourceTemplate ()
+ {
+ IO (Decode16, 0x02E0, 0x02E0, 0x08, 0x08)
+ //IRQNoFlags () {10}
+ IRQ (Edge, ActiveHigh, Exclusive) {6}
+ })
+
+ Name (_PRS, ResourceTemplate ()
+ {
+ IO (Decode16, 0x02E0, 0x02E0, 0x08, 0x08)
+ //IRQNoFlags () {10}
+ IRQ (Edge, ActiveHigh, Exclusive) {6}
+ })
+ }
+#endif
+
+}
diff --git a/src/mainboard/kontron/bSC2/acpi_tables.c b/src/mainboard/kontron/bSC2/acpi_tables.c
new file mode 100644
index 0000000..b7f2730
--- /dev/null
+++ b/src/mainboard/kontron/bSC2/acpi_tables.c
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi_gnvs.h>
+#include <southbridge/intel/bd82x6x/nvs.h>
+//#include "thermal.h"
+
+/* FIXME: check this function. */
+void acpi_create_gnvs(struct global_nvs *gnvs)
+{
+ /* The lid is open by default. */
+ gnvs->lids = 1;
+
+ /* Temperature at which OS will shutdown */
+ gnvs->tcrt = 100;
+ /* Temperature at which OS will throttle CPU */
+ gnvs->tpsv = 90;
+}
diff --git a/src/mainboard/kontron/bSC2/board_info.txt b/src/mainboard/kontron/bSC2/board_info.txt
new file mode 100644
index 0000000..2b0447b
--- /dev/null
+++ b/src/mainboard/kontron/bSC2/board_info.txt
@@ -0,0 +1,6 @@
+Category: half
+ROM protocol: SPI
+ROM package: 8-pin SOIC
+ROM socketed: n
+Flashrom support: n
+Release year: 2011
diff --git a/src/mainboard/kontron/bSC2/cmos.default b/src/mainboard/kontron/bSC2/cmos.default
new file mode 100644
index 0000000..fa9887f
--- /dev/null
+++ b/src/mainboard/kontron/bSC2/cmos.default
@@ -0,0 +1,7 @@
+boot_option=Fallback
+debug_level=Debug
+gfx_uma_size=128M
+nmi=Enable
+power_on_after_fail=Disable
+sata_mode=AHCI
+hyper_threading=Enable
diff --git a/src/mainboard/kontron/bSC2/cmos.layout b/src/mainboard/kontron/bSC2/cmos.layout
new file mode 100644
index 0000000..8f6ae54
--- /dev/null
+++ b/src/mainboard/kontron/bSC2/cmos.layout
@@ -0,0 +1,124 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007-2008 coresystems GmbH
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+# -----------------------------------------------------------------
+entries
+
+# -----------------------------------------------------------------
+# Status Register A
+# -----------------------------------------------------------------
+# Status Register B
+# -----------------------------------------------------------------
+# Status Register C
+#96 4 r 0 status_c_rsvd
+#100 1 r 0 uf_flag
+#101 1 r 0 af_flag
+#102 1 r 0 pf_flag
+#103 1 r 0 irqf_flag
+# -----------------------------------------------------------------
+# Status Register D
+#104 7 r 0 status_d_rsvd
+#111 1 r 0 valid_cmos_ram
+# -----------------------------------------------------------------
+# Diagnostic Status Register
+#112 8 r 0 diag_rsvd1
+
+# -----------------------------------------------------------------
+0 120 r 0 reserved_memory
+#120 264 r 0 unused
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384 1 e 3 boot_option
+385 3 r 0 reserved
+388 4 h 0 reboot_counter
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+#392 3 r 0 unused
+395 4 e 5 debug_level
+#399 1 r 0 unused
+
+# coreboot config options: cpu
+400 1 e 2 hyper_threading
+401 3 e 9 gfx_uma_size
+#404 4 r 0 unused
+
+# coreboot config options: southbridge
+408 1 e 1 nmi
+409 2 e 10 power_on_after_fail
+411 1 e 8 sata_mode
+#412 4 r 0 unused
+
+# coreboot config options: bootloader
+416 424 s 0 boot_devices
+840 8 h 0 boot_default
+848 1 e 7 cmos_defaults_loaded
+#851 5 r 0 unused
+
+# coreboot config options: mainboard specific options
+#856 40 r 0 unused
+
+# SandyBridge MRC Scrambler Seed values
+896 32 r 0 mrc_scrambler_seed
+928 32 r 0 mrc_scrambler_seed_s3
+960 16 r 0 mrc_scrambler_seed_chk
+#976 8 r 0 unused
+
+# coreboot config options: check sums
+984 16 h 0 check_sum
+#1000 24 r 0 amd_reserved
+
+# -----------------------------------------------------------------
+
+enumerations
+
+#ID value text
+1 0 Disable
+1 1 Enable
+2 0 Enable
+2 1 Disable
+3 0 Fallback
+3 1 Normal
+5 0 Emergency
+5 1 Alert
+5 2 Critical
+5 3 Error
+5 4 Warning
+5 5 Notice
+5 6 Info
+5 7 Debug
+5 8 Spew
+6 0 Disable
+6 1 Enable
+6 2 Keep
+7 0 No
+7 1 Yes
+8 0 AHCI
+8 1 Compatible
+9 0 32M
+9 1 64M
+9 2 96M
+9 3 128M
+9 4 160M
+9 5 192M
+9 6 224M
+10 0 Disable
+10 1 Enable
+10 2 Keep
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 895 984
diff --git a/src/mainboard/kontron/bSC2/devicetree.cb b/src/mainboard/kontron/bSC2/devicetree.cb
new file mode 100644
index 0000000..018b72a
--- /dev/null
+++ b/src/mainboard/kontron/bSC2/devicetree.cb
@@ -0,0 +1,126 @@
+chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply.
+
+ register "gfx" = "GMA_STATIC_DISPLAYS(1)"
+ register "gpu_cpu_backlight" = "0x00000000"
+ register "gpu_dp_b_hotplug" = "4"
+ register "gpu_dp_c_hotplug" = "4"
+ register "gpu_dp_d_hotplug" = "4"
+ register "gpu_panel_port_select" = "0"
+ register "gpu_panel_power_backlight_off_delay" = "2000"
+ register "gpu_panel_power_backlight_on_delay" = "2000"
+ register "gpu_panel_power_cycle_delay" = "4"
+ register "gpu_panel_power_down_delay" = "500"
+ register "gpu_panel_power_up_delay" = "100"
+ register "gpu_pch_backlight" = "0x13121312"
+
+ device cpu_cluster 0x0 on
+ chip cpu/intel/model_206ax # FIXME: check all registers
+ register "c1_acpower" = "1"
+ register "c1_battery" = "1"
+ register "c2_acpower" = "3"
+ register "c2_battery" = "3"
+ register "c3_acpower" = "5"
+ register "c3_battery" = "5"
+ device lapic 0x0 on end
+ device lapic 0xacac off end
+ end
+ end
+ device domain 0x0 on
+ chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
+
+ register "c2_latency" = "0x0065"
+ register "docking_supported" = "0"
+ register "gen1_dec" = "0x00fc0a01" # SIO Runtime registers I/O range forwarded to LPC
+ register "gen2_dec" = "0x000403e9" # COM3 I/O range forwarded to LPC
+ register "gen3_dec" = "0x000402e1" # COM4 I/O range forwarded to LPC
+ register "gen4_dec" = "0x000403e9"
+ register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }"
+ register "pcie_port_coalesce" = "1"
+ register "sata_interface_speed_support" = "0x3"
+ register "sata_port_map" = "0x1"
+ register "spi_lvscc" = "0x2005"
+ register "spi_uvscc" = "0x2005"
+
+ device pci 16.0 on # Management Engine Interface 1
+ subsystemid 0x8086 0x1c3a
+ end
+ device pci 16.1 off end # Management Engine Interface 2
+ device pci 16.2 off end # Management Engine IDE-R
+ device pci 16.3 off end # Management Engine KT
+ device pci 19.0 on end # Intel Gigabit Ethernet
+ device pci 1a.0 on # USB2 EHCI #2
+ subsystemid 0x8086 0x1c2d
+ end
+ device pci 1b.0 off end # High Definition Audio
+ device pci 1c.0 on # PCIe Port #1
+ subsystemid 0x8086 0x1c10
+ end
+ device pci 1c.1 on # PCIe Port #2: i82574
+ subsystemid 0x8086 0x1c12
+ end
+ device pci 1c.2 on # PCIe Port #3: OXPCIE958
+ subsystemid 0x8086 0x1c14
+ end
+ device pci 1c.3 off end # PCIe Port #4
+ device pci 1c.4 off end # PCIe Port #5
+ device pci 1c.5 off end # PCIe Port #6, 0x8086 0x1c1a: JMB368
+ device pci 1c.6 off end # PCIe Port #7, 0x8086 0x1c1c: PEX8112
+ device pci 1c.7 off end # PCIe Port #8, already in use by GB LAN
+ device pci 1d.0 on # USB2 EHCI #1
+ subsystemid 0x8086 0x1c26
+ end
+ device pci 1e.0 off end # PCI bridge
+ device pci 1f.0 on # LPC bridge
+ subsystemid 0x8086 0x1c4f
+ chip superio/smsc/smscsuperio
+ device pnp 2e.0 off end # Floppy
+ device pnp 2e.3 off end # Parallel Port
+ device pnp 2e.4 on # COM1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.5 on # COM2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.7 on # PS2 Keyboard & Mouse
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ irq 0x72 = 12
+ end
+ device pnp 2e.a on # Runtime Regs
+ io 0x60 = 0x0a00
+ drq 0xF0 = 0x0b # no 32kHz
+ end
+ device pnp 2e.b on # COM3
+ io 0x60 = 0x3e8
+ irq 0x70 = 5
+ end
+ device pnp 2e.c on # COM4
+ io 0x60 = 0x2e0
+ irq 0x70 = 6
+ end
+ end # smscsuperio
+ end
+ device pci 1f.2 on # SATA Controller 1
+ subsystemid 0x8086 0x1c01
+ end
+ device pci 1f.3 on # SMBus
+ subsystemid 0x8086 0x1c22
+ end
+ device pci 1f.5 off end # SATA Controller 2, subsystemid 0x8086 0x1c09
+ device pci 1f.6 off end # Thermal
+
+ end
+ device pci 00.0 on # Host bridge
+ subsystemid 0x8086 0x0104
+ end
+ device pci 01.0 on # PEG
+ subsystemid 0x8086 0x0101
+ end
+ device pci 02.0 on # iGPU
+ subsystemid 0x8086 0x2010
+ end
+ end
+end
diff --git a/src/mainboard/kontron/bSC2/devicetree.cb.orig b/src/mainboard/kontron/bSC2/devicetree.cb.orig
new file mode 100644
index 0000000..39214f9
--- /dev/null
+++ b/src/mainboard/kontron/bSC2/devicetree.cb.orig
@@ -0,0 +1,109 @@
+chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply.
+ register "gfx" = "GMA_STATIC_DISPLAYS(1)"
+ register "gpu_cpu_backlight" = "0x00000000"
+ register "gpu_dp_b_hotplug" = "4"
+ register "gpu_dp_c_hotplug" = "4"
+ register "gpu_dp_d_hotplug" = "4"
+ register "gpu_panel_port_select" = "0"
+ register "gpu_panel_power_backlight_off_delay" = "2000"
+ register "gpu_panel_power_backlight_on_delay" = "2000"
+ register "gpu_panel_power_cycle_delay" = "4"
+ register "gpu_panel_power_down_delay" = "500"
+ register "gpu_panel_power_up_delay" = "100"
+ register "gpu_pch_backlight" = "0x13121312"
+ device cpu_cluster 0x0 on
+ chip cpu/intel/model_206ax # FIXME: check all registers
+ register "c1_acpower" = "1"
+ register "c1_battery" = "1"
+ register "c2_acpower" = "3"
+ register "c2_battery" = "3"
+ register "c3_acpower" = "5"
+ register "c3_battery" = "5"
+ device lapic 0x0 on
+ end
+ device lapic 0xacac off
+ end
+ end
+ end
+ device domain 0x0 on
+ chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
+ register "c2_latency" = "0x0065"
+ register "docking_supported" = "0"
+ register "gen1_dec" = "0x00fc0a01"
+ register "gen2_dec" = "0x000403e9"
+ register "gen3_dec" = "0x000402e1"
+ register "gen4_dec" = "0x000403e9"
+ register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }"
+ register "pcie_port_coalesce" = "1"
+ register "sata_interface_speed_support" = "0x3"
+ register "sata_port_map" = "0x1"
+ register "spi_lvscc" = "0x2005"
+ register "spi_uvscc" = "0x2005"
+ device pci 16.0 on # Management Engine Interface 1
+ subsystemid 0x8086 0x1c3a
+ end
+ device pci 16.1 off # Management Engine Interface 2
+ end
+ device pci 16.2 off # Management Engine IDE-R
+ end
+ device pci 16.3 off # Management Engine KT
+ end
+ device pci 19.0 on # Intel Gigabit Ethernet
+ end
+ device pci 1a.0 on # USB2 EHCI #2
+ subsystemid 0x8086 0x1c2d
+ end
+ device pci 1b.0 off # High Definition Audio
+ end
+ device pci 1c.0 on # PCIe Port #1
+ subsystemid 0x8086 0x1c10
+ end
+ device pci 1c.1 on # PCIe Port #2
+ subsystemid 0x8086 0x1c12
+ end
+ device pci 1c.2 on # PCIe Port #3
+ subsystemid 0x8086 0x1c14
+ end
+ device pci 1c.3 off # PCIe Port #4
+ end
+ device pci 1c.4 off # PCIe Port #5
+ end
+ device pci 1c.5 on # PCIe Port #6
+ subsystemid 0x8086 0x1c1a
+ end
+ device pci 1c.6 on # PCIe Port #7
+ subsystemid 0x8086 0x1c1c
+ end
+ device pci 1c.7 off # PCIe Port #8
+ end
+ device pci 1d.0 on # USB2 EHCI #1
+ subsystemid 0x8086 0x1c26
+ end
+ device pci 1e.0 off # PCI bridge
+ end
+ device pci 1f.0 on # LPC bridge
+ subsystemid 0x8086 0x1c4f
+ end
+ device pci 1f.2 on # SATA Controller 1
+ subsystemid 0x8086 0x1c01
+ end
+ device pci 1f.3 on # SMBus
+ subsystemid 0x8086 0x1c22
+ end
+ device pci 1f.5 on # SATA Controller 2 Unsupported PCI device 8086:1c09
+ subsystemid 0x8086 0x1c09
+ end
+ device pci 1f.6 off # Thermal
+ end
+ end
+ device pci 00.0 on # Host bridge Host bridge
+ subsystemid 0x8086 0x0104
+ end
+ device pci 01.0 on # PEG
+ subsystemid 0x8086 0x0101
+ end
+ device pci 02.0 on # iGPU
+ subsystemid 0x8086 0x2010
+ end
+ end
+end
diff --git a/src/mainboard/kontron/bSC2/dsdt.asl b/src/mainboard/kontron/bSC2/dsdt.asl
new file mode 100644
index 0000000..e648a99
--- /dev/null
+++ b/src/mainboard/kontron/bSC2/dsdt.asl
@@ -0,0 +1,28 @@
+#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
+#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
+
+
+#include <acpi/acpi.h>
+
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ 0x02, /* DSDT revision: ACPI 2.0 and up */
+ OEM_ID,
+ ACPI_TABLE_CREATOR,
+ 0x20141018 /* OEM revision */
+)
+{
+ #include "acpi/platform.asl"
+ #include <cpu/intel/common/acpi/cpu.asl>
+ #include <southbridge/intel/common/acpi/platform.asl>
+ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
+ #include <southbridge/intel/common/acpi/sleepstates.asl>
+
+ Device (\_SB.PCI0)
+ {
+ #include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
+ #include <drivers/intel/gma/acpi/default_brightness_levels.asl>
+ #include <southbridge/intel/bd82x6x/acpi/pch.asl>
+ }
+}
diff --git a/src/mainboard/kontron/bSC2/early_init.c b/src/mainboard/kontron/bSC2/early_init.c
new file mode 100644
index 0000000..f53b749
--- /dev/null
+++ b/src/mainboard/kontron/bSC2/early_init.c
@@ -0,0 +1,47 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+
+#include <bootblock_common.h>
+#include <device/pci_ops.h>
+#include <northbridge/intel/sandybridge/sandybridge.h>
+#include <northbridge/intel/sandybridge/raminit_native.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <superio/smsc/smscsuperio/smscsuperio.h>
+
+#define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1)
+
+const struct southbridge_usb_port mainboard_usb_ports[] = {
+/* enabled, power, oc pin */
+ { 1, 1, 0 }, /* P0: USB0 */
+ { 1, 1, 0 }, /* P1: USB1 */
+ { 1, 1, 1 }, /* P2: USB2 */
+ { 1, 1, 1 }, /* P3: USB3 */
+ { 0, 0, -1 }, /* P4: - */
+ { 0, 0, -1 }, /* P5: - */
+ { 0, 0, -1 }, /* P6: - */
+ { 0, 0, -1 }, /* P7: - */
+ { 1, 1, 4 }, /* P8: USB4 */
+ { 1, 1, 4 }, /* P9: USB5 */
+ { 1, 0, 5 }, /* P10: USB6 */
+ { 1, 0, 5 }, /* P11: USB7 */
+ { 0, 0, -1 }, /* P12: - */
+ { 0, 0, -1 }, /* P13: - */
+};
+
+void bootblock_mainboard_early_init(void)
+{
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x1403); /* COMA, COMB, KBC and LPC 0x2E enabled */
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010); /* LPC decode ranges COMA=3F8, COMB=2F8 */
+}
+
+void mainboard_early_init(int s3resume)
+{
+ smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+}
+
+/* SPD map */
+void mainboard_get_spd(spd_raw_data *spd, bool id_only)
+{
+ read_spd(&spd[0], 0x50, id_only); /* Read Dimm1 RAM settings */
+ read_spd(&spd[2], 0x52, id_only); /* Read Dimm2 RAM settings */
+}
diff --git a/src/mainboard/kontron/bSC2/gma-mainboard.ads b/src/mainboard/kontron/bSC2/gma-mainboard.ads
new file mode 100644
index 0000000..8bfbab6
--- /dev/null
+++ b/src/mainboard/kontron/bSC2/gma-mainboard.ads
@@ -0,0 +1,23 @@
+-- SPDX-License-Identifier: GPL-2.0-or-later
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+ -- FIXME: check this
+ ports : constant Port_List :=
+ (LVDS,
+ DP1,
+ DP2,
+ DP3,
+ HDMI1,
+ HDMI2,
+ HDMI3,
+ Analog,
+ others => Disabled);
+
+end GMA.Mainboard;
diff --git a/src/mainboard/kontron/bSC2/gma-mainboard.ads.orig b/src/mainboard/kontron/bSC2/gma-mainboard.ads.orig
new file mode 100644
index 0000000..133fde5
--- /dev/null
+++ b/src/mainboard/kontron/bSC2/gma-mainboard.ads.orig
@@ -0,0 +1,23 @@
+-- SPDX-License-Identifier: GPL-2.0-or-later
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+ -- FIXME: check this
+ ports : constant Port_List :=
+ (DP1,
+ DP2,
+ DP3,
+ HDMI1,
+ HDMI2,
+ HDMI3,
+ Analog,
+ LVDS,
+ eDP);
+
+end GMA.Mainboard;
diff --git a/src/mainboard/kontron/bSC2/gpio.c b/src/mainboard/kontron/bSC2/gpio.c
new file mode 100644
index 0000000..e93e29f
--- /dev/null
+++ b/src/mainboard/kontron/bSC2/gpio.c
@@ -0,0 +1,232 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+ .gpio0 = GPIO_MODE_GPIO,
+ .gpio1 = GPIO_MODE_GPIO,
+ .gpio2 = GPIO_MODE_GPIO,
+ .gpio3 = GPIO_MODE_GPIO,
+ .gpio4 = GPIO_MODE_GPIO,
+ .gpio5 = GPIO_MODE_GPIO,
+ .gpio6 = GPIO_MODE_GPIO,
+ .gpio7 = GPIO_MODE_GPIO,
+ .gpio8 = GPIO_MODE_GPIO,
+ .gpio9 = GPIO_MODE_NATIVE,
+ .gpio10 = GPIO_MODE_GPIO,
+ .gpio11 = GPIO_MODE_GPIO,
+ .gpio12 = GPIO_MODE_NATIVE,
+ .gpio13 = GPIO_MODE_GPIO,
+ .gpio14 = GPIO_MODE_GPIO,
+ .gpio15 = GPIO_MODE_GPIO,
+ .gpio16 = GPIO_MODE_GPIO,
+ .gpio17 = GPIO_MODE_GPIO,
+ .gpio18 = GPIO_MODE_GPIO,
+ .gpio19 = GPIO_MODE_GPIO,
+ .gpio20 = GPIO_MODE_GPIO,
+ .gpio21 = GPIO_MODE_GPIO,
+ .gpio22 = GPIO_MODE_GPIO,
+ .gpio23 = GPIO_MODE_NATIVE,
+ .gpio24 = GPIO_MODE_GPIO,
+ .gpio25 = GPIO_MODE_GPIO,
+ .gpio26 = GPIO_MODE_GPIO,
+ .gpio27 = GPIO_MODE_GPIO,
+ .gpio28 = GPIO_MODE_GPIO,
+ .gpio29 = GPIO_MODE_GPIO,
+ .gpio30 = GPIO_MODE_NATIVE,
+ .gpio31 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+ .gpio0 = GPIO_DIR_INPUT,
+ .gpio1 = GPIO_DIR_INPUT,
+ .gpio2 = GPIO_DIR_INPUT,
+ .gpio3 = GPIO_DIR_INPUT,
+ .gpio4 = GPIO_DIR_INPUT,
+ .gpio5 = GPIO_DIR_INPUT,
+ .gpio6 = GPIO_DIR_INPUT,
+ .gpio7 = GPIO_DIR_INPUT,
+ .gpio8 = GPIO_DIR_OUTPUT,
+ .gpio10 = GPIO_DIR_OUTPUT,
+ .gpio11 = GPIO_DIR_INPUT,
+ .gpio13 = GPIO_DIR_INPUT,
+ .gpio14 = GPIO_DIR_OUTPUT,
+ .gpio15 = GPIO_DIR_OUTPUT,
+ .gpio16 = GPIO_DIR_OUTPUT,
+ .gpio17 = GPIO_DIR_OUTPUT,
+ .gpio18 = GPIO_DIR_OUTPUT,
+ .gpio19 = GPIO_DIR_INPUT,
+ .gpio20 = GPIO_DIR_OUTPUT,
+ .gpio21 = GPIO_DIR_OUTPUT,
+ .gpio22 = GPIO_DIR_INPUT,
+ .gpio24 = GPIO_DIR_OUTPUT,
+ .gpio25 = GPIO_DIR_OUTPUT,
+ .gpio26 = GPIO_DIR_OUTPUT,
+ .gpio27 = GPIO_DIR_INPUT,
+ .gpio28 = GPIO_DIR_INPUT,
+ .gpio29 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+ .gpio8 = GPIO_LEVEL_LOW,
+ .gpio10 = GPIO_LEVEL_LOW,
+ .gpio14 = GPIO_LEVEL_LOW,
+ .gpio15 = GPIO_LEVEL_LOW,
+ .gpio16 = GPIO_LEVEL_LOW,
+ .gpio17 = GPIO_LEVEL_LOW,
+ .gpio18 = GPIO_LEVEL_LOW,
+ .gpio20 = GPIO_LEVEL_LOW,
+ .gpio21 = GPIO_LEVEL_LOW,
+ .gpio24 = GPIO_LEVEL_LOW,
+ .gpio25 = GPIO_LEVEL_LOW,
+ .gpio26 = GPIO_LEVEL_HIGH,
+ .gpio29 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
+ .gpio30 = GPIO_RESET_RSMRST,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+ .gpio4 = GPIO_INVERT,
+ .gpio5 = GPIO_INVERT,
+ .gpio6 = GPIO_INVERT,
+ .gpio7 = GPIO_INVERT,
+ .gpio11 = GPIO_INVERT,
+ .gpio13 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+ .gpio32 = GPIO_MODE_NATIVE,
+ .gpio33 = GPIO_MODE_GPIO,
+ .gpio34 = GPIO_MODE_NATIVE,
+ .gpio35 = GPIO_MODE_GPIO,
+ .gpio36 = GPIO_MODE_GPIO,
+ .gpio37 = GPIO_MODE_GPIO,
+ .gpio38 = GPIO_MODE_GPIO,
+ .gpio39 = GPIO_MODE_GPIO,
+ .gpio40 = GPIO_MODE_NATIVE,
+ .gpio41 = GPIO_MODE_NATIVE,
+ .gpio42 = GPIO_MODE_NATIVE,
+ .gpio43 = GPIO_MODE_NATIVE,
+ .gpio44 = GPIO_MODE_GPIO,
+ .gpio45 = GPIO_MODE_GPIO,
+ .gpio46 = GPIO_MODE_NATIVE,
+ .gpio47 = GPIO_MODE_GPIO,
+ .gpio48 = GPIO_MODE_GPIO,
+ .gpio49 = GPIO_MODE_GPIO,
+ .gpio50 = GPIO_MODE_GPIO,
+ .gpio51 = GPIO_MODE_GPIO,
+ .gpio52 = GPIO_MODE_GPIO,
+ .gpio53 = GPIO_MODE_GPIO,
+ .gpio54 = GPIO_MODE_GPIO,
+ .gpio55 = GPIO_MODE_GPIO,
+ .gpio56 = GPIO_MODE_GPIO,
+ .gpio57 = GPIO_MODE_GPIO,
+ .gpio58 = GPIO_MODE_NATIVE,
+ .gpio59 = GPIO_MODE_NATIVE,
+ .gpio60 = GPIO_MODE_GPIO,
+ .gpio61 = GPIO_MODE_NATIVE,
+ .gpio62 = GPIO_MODE_NATIVE,
+ .gpio63 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+ .gpio33 = GPIO_DIR_OUTPUT,
+ .gpio35 = GPIO_DIR_INPUT,
+ .gpio36 = GPIO_DIR_INPUT,
+ .gpio37 = GPIO_DIR_INPUT,
+ .gpio38 = GPIO_DIR_INPUT,
+ .gpio39 = GPIO_DIR_INPUT,
+ .gpio44 = GPIO_DIR_INPUT,
+ .gpio45 = GPIO_DIR_INPUT,
+ .gpio47 = GPIO_DIR_INPUT,
+ .gpio48 = GPIO_DIR_INPUT,
+ .gpio49 = GPIO_DIR_INPUT,
+ .gpio50 = GPIO_DIR_OUTPUT,
+ .gpio51 = GPIO_DIR_INPUT,
+ .gpio52 = GPIO_DIR_OUTPUT,
+ .gpio53 = GPIO_DIR_OUTPUT,
+ .gpio54 = GPIO_DIR_INPUT,
+ .gpio55 = GPIO_DIR_INPUT,
+ .gpio56 = GPIO_DIR_INPUT,
+ .gpio57 = GPIO_DIR_INPUT,
+ .gpio60 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+ .gpio33 = GPIO_LEVEL_LOW,
+ .gpio50 = GPIO_LEVEL_LOW,
+ .gpio52 = GPIO_LEVEL_LOW,
+ .gpio53 = GPIO_LEVEL_LOW,
+ .gpio60 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
+ .gpio64 = GPIO_MODE_NATIVE,
+ .gpio65 = GPIO_MODE_GPIO,
+ .gpio66 = GPIO_MODE_GPIO,
+ .gpio67 = GPIO_MODE_GPIO,
+ .gpio68 = GPIO_MODE_GPIO,
+ .gpio69 = GPIO_MODE_GPIO,
+ .gpio70 = GPIO_MODE_GPIO,
+ .gpio71 = GPIO_MODE_GPIO,
+ .gpio72 = GPIO_MODE_NATIVE,
+ .gpio73 = GPIO_MODE_GPIO,
+ .gpio74 = GPIO_MODE_NATIVE,
+ .gpio75 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
+ .gpio65 = GPIO_DIR_OUTPUT,
+ .gpio66 = GPIO_DIR_OUTPUT,
+ .gpio67 = GPIO_DIR_OUTPUT,
+ .gpio68 = GPIO_DIR_OUTPUT,
+ .gpio69 = GPIO_DIR_OUTPUT,
+ .gpio70 = GPIO_DIR_OUTPUT,
+ .gpio71 = GPIO_DIR_OUTPUT,
+ .gpio73 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
+ .gpio65 = GPIO_LEVEL_LOW,
+ .gpio66 = GPIO_LEVEL_LOW,
+ .gpio67 = GPIO_LEVEL_LOW,
+ .gpio68 = GPIO_LEVEL_HIGH,
+ .gpio69 = GPIO_LEVEL_HIGH,
+ .gpio70 = GPIO_LEVEL_LOW,
+ .gpio71 = GPIO_LEVEL_LOW,
+ .gpio73 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+ .set1 = {
+ .mode = &pch_gpio_set1_mode,
+ .direction = &pch_gpio_set1_direction,
+ .level = &pch_gpio_set1_level,
+ .blink = &pch_gpio_set1_blink,
+ .invert = &pch_gpio_set1_invert,
+ .reset = &pch_gpio_set1_reset,
+ },
+ .set2 = {
+ .mode = &pch_gpio_set2_mode,
+ .direction = &pch_gpio_set2_direction,
+ .level = &pch_gpio_set2_level,
+ .reset = &pch_gpio_set2_reset,
+ },
+ .set3 = {
+ .mode = &pch_gpio_set3_mode,
+ .direction = &pch_gpio_set3_direction,
+ .level = &pch_gpio_set3_level,
+ .reset = &pch_gpio_set3_reset,
+ },
+};
diff --git a/src/mainboard/kontron/bSC2/hda_verb.c b/src/mainboard/kontron/bSC2/hda_verb.c
new file mode 100644
index 0000000..3804740
--- /dev/null
+++ b/src/mainboard/kontron/bSC2/hda_verb.c
@@ -0,0 +1,40 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2014 Vladimir Serbinenko
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+ 0x80862805, /* Codec Vendor / Device ID: Intel */
+ 0x80860101, /* Subsystem ID */
+
+ 0x00000004, /* Number of 4 dword sets */
+ /* NID 0x01: Subsystem ID. */
+ AZALIA_SUBVENDOR(0x3, 0x80860101),
+
+ /* NID 0x05. */
+ AZALIA_PIN_CFG(0x3, 0x05, 0x18560010),
+
+ /* NID 0x06. */
+ AZALIA_PIN_CFG(0x3, 0x06, 0x18560020),
+
+ /* NID 0x07. */
+ AZALIA_PIN_CFG(0x3, 0x07, 0x18560030),
+};
+
+const u32 pc_beep_verbs[0] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/kontron/bSC2/mainboard.c b/src/mainboard/kontron/bSC2/mainboard.c
new file mode 100644
index 0000000..1b9cd36
--- /dev/null
+++ b/src/mainboard/kontron/bSC2/mainboard.c
@@ -0,0 +1,139 @@
+#include <device/device.h>
+#include <drivers/intel/gma/int15.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <console/console.h>
+#include <device/pnp_ops.h>
+#include <device/smbus_host.h>
+
+/* SCH3114 */
+#define SIO_RUNTIME_BASE 0x0A00
+
+/* CPLD */
+#define CPLD_IDX 0x0A80
+#define CPLD_DATA (CPLD_IDX + 1)
+#define I2C_PRER_LO_IDX 0x0B
+#define I2C_CTR_IDX 0x0D
+#define CFG_CPLD 0x37
+
+/* ADT7490 */
+#define SMBUS_IO_BASE 0x0400
+#define ADT7490_ADDRESS 0x2E
+#define REG_VENDID 0x3E
+#define REG_DEVID2 0x3F
+#define PWM1_DUTY_CYCLE 0x30
+#define PECI_TCON_LIMIT 0x3D
+#define CONF_REG_1 0x40
+#define PWM1_CONF_REG 0x5C
+#define R2_TRAN_PWM3_FREQ 0x61
+#define PWM1_MIN_DUTY_CYCLE 0x64
+#define PWM3_MIN_DUTY_CYCLE 0x66
+#define R2_TEMP_TMIN 0x69
+#define INT_MASK_1 0x74
+#define INT_MASK_2 0x75
+#define THERM_TIMER_LIMIT 0x7A
+#define INT_MASK_3 0x82
+#define INT_MASK_4 0x83
+
+static u32 smbus_io_base = SMBUS_IO_BASE;
+static u32 adt7490_address = ADT7490_ADDRESS;
+
+#define adt7490_read_byte(reg) do_smbus_read_byte(smbus_io_base, adt7490_address, reg)
+#define adt7490_write_byte(reg, val) do_smbus_write_byte(smbus_io_base, adt7490_address, reg, val)
+
+/* CPLD I/O operations */
+//static u8 cpld_read8(u8 idx)
+//{
+// outb(idx, CPLD_IDX);
+// return inb(CPLD_DATA);
+//}
+
+//static u16 cpld_read16(u8 idx)
+//{
+// return cpld_read8(idx) | (cpld_read8(idx + 1) << 8);
+//}
+
+static void cpld_write8(u8 idx, u8 value)
+{
+ outb(idx, CPLD_IDX);
+ outb(value, CPLD_DATA);
+}
+
+static void cpld_write16(u8 idx, u16 value)
+{
+ cpld_write8(idx, (u8)value);
+ cpld_write8(idx + 1, (u8)(value >> 8));
+}
+
+/* SCH3114 SIO GPIOs. */
+static const u16 sio_init_table[] = { // nibble: hi = offset, lo = value
+
+ // GP5x = COM2 function instead of GPIO
+ 0x3F05, 0x4005, 0x4105, 0x4204, 0x4305, 0x4404, 0x4505, 0x4604,
+
+ // GP1x = COM3 function instead of GPIO
+ 0x2305, 0x2404, 0x2505, 0x2605, 0x2705, 0x2904, 0x2A05, 0x2B04,
+
+ // GP6x = COM4 function instead of GPIO
+ 0x3405, 0x3704, 0x5405, 0x5505, 0x5605, 0x5704, 0x5805, 0x5904,
+};
+
+static void mainboard_init(struct device *dev)
+{
+ int i;
+ /* Init SCH311x SIO GPIOs. */
+ printk(BIOS_DEBUG, "Init SIO GPIOs @ 0x%04x\n", SIO_RUNTIME_BASE);
+ for (i = 0; i < ARRAY_SIZE(sio_init_table); i++) {
+ u16 val = sio_init_table[i];
+ outb((u8)val, SIO_RUNTIME_BASE + (val >> 8));
+ }
+
+ /* Init CPLD */
+ cpld_write16(I2C_PRER_LO_IDX, 0x020); // I2C Clock prescaler
+ cpld_write8(I2C_CTR_IDX, 0x80); // I2C Clock control
+
+ /* Init ADT7490 */
+ int vendid, devid2;
+
+ vendid = adt7490_read_byte(REG_VENDID); /* Read VEN & DEV ID */
+ devid2 = adt7490_read_byte(REG_DEVID2);
+
+ /* If ADT7490 is present, then initialize it, else exit */
+ if ((vendid = 0x41) && // Analog Devices
+ (devid2 & 0xfc) == 0x6c) { // Device ID
+
+ printk(BIOS_DEBUG, "Found ADT7490 at %x:%x\n", smbus_io_base, adt7490_address);
+
+ adt7490_write_byte(PWM1_DUTY_CYCLE, 0x81); // Half Duty
+ adt7490_write_byte(PECI_TCON_LIMIT, 0x80); // Disabled
+ adt7490_write_byte(CONF_REG_1, 0x15); // Monitoring and PWM control outputs enabled
+ adt7490_write_byte(PWM1_CONF_REG, 0x42); // 250ms spin time, Remote 2 temp. controls PWM1
+ adt7490_write_byte(R2_TRAN_PWM3_FREQ, 0xB4); // Frequency = 35.3 Hz, low frequency PWM mode,
+ // 26.67 C parameter.
+ adt7490_write_byte(PWM1_MIN_DUTY_CYCLE, 0x54);
+ adt7490_write_byte(PWM3_MIN_DUTY_CYCLE, 0x8C);
+ adt7490_write_byte(R2_TEMP_TMIN, 0x37); // When the temperature measured exceeds T MIN , the
+ // appropriate fan runs at minimum speed and
+ // increases with temperature according to T RANGE.
+ adt7490_write_byte(INT_MASK_1, 0xFF); // Mask all #SMBALERT
+ adt7490_write_byte(INT_MASK_2, 0xFF); // Mask all #SMBALERT
+ adt7490_write_byte(THERM_TIMER_LIMIT, 0xFF); // Avoid unwanted alerts from being generated.
+ adt7490_write_byte(INT_MASK_3, 0xFF); // Mask all #SMBALERT
+ adt7490_write_byte(INT_MASK_4, 0xF8); // Mask all #SMBALERT
+
+ }
+
+}
+
+static void mainboard_enable(struct device *dev)
+{
+ dev->ops->init = mainboard_init;
+
+ /* FIXME: fix these values. */
+ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS,
+ GMA_INT15_PANEL_FIT_DEFAULT,
+ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+};
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