Attention is currently required from: Raul Rangel, Nico Huber, Michał Żygowski, Reka Norman, Michał Kopeć, Angel Pons, Arthur Heymans, Felix Held.
will this config also helps Xeon platforms?
It should help all Intel platform that supports CLFLUSH IMO.
Well on SPR xeon-sp against recommendations TempRamExit was overloaded with functionality to write things to DRAM to speed things up and therefore made mandatory in the bootflow. CLFLUSHING would have been a way better solution, as invalidating cache in a different environment (FSP) is just though to get right even from a security perspective...
ah, i missed that SPR is still using FSP-T
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