Angel Pons submitted this change.
soc/intel/baytrail: Align whitespace and comments
This reduces the differences between Bay Trail and Braswell.
Tested with BUILD_TIMELESS=1, Google Ninja remains identical.
Change-Id: Idfdb1e6ec9bd0c1a11ef36ce0434ed5e12895187
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43186
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
---
M src/soc/intel/baytrail/acpi/device_nvs.asl
M src/soc/intel/baytrail/acpi/dptf/dptf.asl
M src/soc/intel/baytrail/acpi/globalnvs.asl
M src/soc/intel/baytrail/acpi/irqlinks.asl
M src/soc/intel/baytrail/acpi/irqroute.asl
M src/soc/intel/baytrail/acpi/lpc.asl
M src/soc/intel/baytrail/acpi/platform.asl
M src/soc/intel/baytrail/acpi/southcluster.asl
M src/soc/intel/baytrail/bootblock/bootblock.c
M src/soc/intel/baytrail/cpu.c
M src/soc/intel/baytrail/include/soc/device_nvs.h
M src/soc/intel/baytrail/include/soc/iosf.h
M src/soc/intel/baytrail/include/soc/irq.h
M src/soc/intel/baytrail/include/soc/nvs.h
M src/soc/intel/baytrail/include/soc/pattrs.h
M src/soc/intel/baytrail/include/soc/pm.h
M src/soc/intel/baytrail/lpe.c
M src/soc/intel/baytrail/northcluster.c
M src/soc/intel/baytrail/pmutil.c
M src/soc/intel/baytrail/smihandler.c
M src/soc/intel/baytrail/smm.c
M src/soc/intel/baytrail/southcluster.c
22 files changed, 331 insertions(+), 305 deletions(-)
diff --git a/src/soc/intel/baytrail/acpi/device_nvs.asl b/src/soc/intel/baytrail/acpi/device_nvs.asl
index 31f18a0..3722856 100644
--- a/src/soc/intel/baytrail/acpi/device_nvs.asl
+++ b/src/soc/intel/baytrail/acpi/device_nvs.asl
@@ -2,67 +2,67 @@
/* Device Enabled in ACPI Mode */
-S0EN, 8, // SDMA Enable
-S1EN, 8, // I2C1 Enable
-S2EN, 8, // I2C2 Enable
-S3EN, 8, // I2C3 Enable
-S4EN, 8, // I2C4 Enable
-S5EN, 8, // I2C5 Enable
-S6EN, 8, // I2C6 Enable
-S7EN, 8, // I2C7 Enable
-S8EN, 8, // SDMA2 Enable
-S9EN, 8, // SPI Enable
-SAEN, 8, // PWM1 Enable
-SBEN, 8, // PWM2 Enable
-SCEN, 8, // UART2 Enable
-SDEN, 8, // UART2 Enable
-C0EN, 8, // MMC Enable
-C1EN, 8, // SDIO Enable
-C2EN, 8, // SD Card Enable
-LPEN, 8, // LPE Enable
+S0EN, 8, /* SDMA Enable */
+S1EN, 8, /* I2C1 Enable */
+S2EN, 8, /* I2C2 Enable */
+S3EN, 8, /* I2C3 Enable */
+S4EN, 8, /* I2C4 Enable */
+S5EN, 8, /* I2C5 Enable */
+S6EN, 8, /* I2C6 Enable */
+S7EN, 8, /* I2C7 Enable */
+S8EN, 8, /* SDMA2 Enable */
+S9EN, 8, /* SPI Enable */
+SAEN, 8, /* PWM1 Enable */
+SBEN, 8, /* PWM2 Enable */
+SCEN, 8, /* UART2 Enable */
+SDEN, 8, /* UART2 Enable */
+C0EN, 8, /* MMC Enable */
+C1EN, 8, /* SDIO Enable */
+C2EN, 8, /* SD Card Enable */
+LPEN, 8, /* LPE Enable */
/* BAR 0 */
-S0B0, 32, // SDMA BAR0
-S1B0, 32, // I2C1 BAR0
-S2B0, 32, // I2C2 BAR0
-S3B0, 32, // I2C3 BAR0
-S4B0, 32, // I2C4 BAR0
-S5B0, 32, // I2C5 BAR0
-S6B0, 32, // I2C6 BAR0
-S7B0, 32, // I2C7 BAR0
-S8B0, 32, // SDMA2 BAR0
-S9B0, 32, // SPI BAR0
-SAB0, 32, // PWM1 BAR0
-SBB0, 32, // PWM2 BAR0
-SCB0, 32, // UART1 BAR0
-SDB0, 32, // UART2 BAR0
-C0B0, 32, // MMC BAR0
-C1B0, 32, // SDIO BAR0
-C2B0, 32, // SD Card BAR0
-LPB0, 32, // LPE BAR0
+S0B0, 32, /* SDMA BAR0 */
+S1B0, 32, /* I2C1 BAR0 */
+S2B0, 32, /* I2C2 BAR0 */
+S3B0, 32, /* I2C3 BAR0 */
+S4B0, 32, /* I2C4 BAR0 */
+S5B0, 32, /* I2C5 BAR0 */
+S6B0, 32, /* I2C6 BAR0 */
+S7B0, 32, /* I2C7 BAR0 */
+S8B0, 32, /* SDMA2 BAR0 */
+S9B0, 32, /* SPI BAR0 */
+SAB0, 32, /* PWM1 BAR0 */
+SBB0, 32, /* PWM2 BAR0 */
+SCB0, 32, /* UART1 BAR0 */
+SDB0, 32, /* UART2 BAR0 */
+C0B0, 32, /* MMC BAR0 */
+C1B0, 32, /* SDIO BAR0 */
+C2B0, 32, /* SD Card BAR0 */
+LPB0, 32, /* LPE BAR0 */
/* BAR 1 */
-S0B1, 32, // SDMA BAR1
-S1B1, 32, // I2C1 BAR1
-S2B1, 32, // I2C2 BAR1
-S3B1, 32, // I2C3 BAR1
-S4B1, 32, // I2C4 BAR1
-S5B1, 32, // I2C5 BAR1
-S6B1, 32, // I2C6 BAR1
-S7B1, 32, // I2C7 BAR1
-S8B1, 32, // SDMA2 BAR1
-S9B1, 32, // SPI BAR1
-SAB1, 32, // PWM1 BAR1
-SBB1, 32, // PWM2 BAR1
-SCB1, 32, // UART1 BAR1
-SDB1, 32, // UART2 BAR1
-C0B1, 32, // MMC BAR1
-C1B1, 32, // SDIO BAR1
-C2B1, 32, // SD Card BAR1
-LPB1, 32, // LPE BAR1
+S0B1, 32, /* SDMA BAR1 */
+S1B1, 32, /* I2C1 BAR1 */
+S2B1, 32, /* I2C2 BAR1 */
+S3B1, 32, /* I2C3 BAR1 */
+S4B1, 32, /* I2C4 BAR1 */
+S5B1, 32, /* I2C5 BAR1 */
+S6B1, 32, /* I2C6 BAR1 */
+S7B1, 32, /* I2C7 BAR1 */
+S8B1, 32, /* SDMA2 BAR1 */
+S9B1, 32, /* SPI BAR1 */
+SAB1, 32, /* PWM1 BAR1 */
+SBB1, 32, /* PWM2 BAR1 */
+SCB1, 32, /* UART1 BAR1 */
+SDB1, 32, /* UART2 BAR1 */
+C0B1, 32, /* MMC BAR1 */
+C1B1, 32, /* SDIO BAR1 */
+C2B1, 32, /* SD Card BAR1 */
+LPB1, 32, /* LPE BAR1 */
/* Extra */
-LPFW, 32, // LPE BAR2 Firmware
+LPFW, 32, /* LPE BAR2 Firmware */
diff --git a/src/soc/intel/baytrail/acpi/dptf/dptf.asl b/src/soc/intel/baytrail/acpi/dptf/dptf.asl
index 68df275..66bfa45 100644
--- a/src/soc/intel/baytrail/acpi/dptf/dptf.asl
+++ b/src/soc/intel/baytrail/acpi/dptf/dptf.asl
@@ -26,7 +26,8 @@
}
}
- /* Arg0: Buffer containing UUID
+ /*
+ * Arg0: Buffer containing UUID
* Arg1: Integer containing Revision ID of buffer format
* Arg2: Integer containing count of entries in Arg3
* Arg3: Buffer containing list of DWORD capabilities
diff --git a/src/soc/intel/baytrail/acpi/globalnvs.asl b/src/soc/intel/baytrail/acpi/globalnvs.asl
index 6cb68ba..c472d06 100644
--- a/src/soc/intel/baytrail/acpi/globalnvs.asl
+++ b/src/soc/intel/baytrail/acpi/globalnvs.asl
@@ -2,56 +2,57 @@
/* Global Variables */
-Name(\PICM, 0) // IOAPIC/8259
+Name(\PICM, 0) /* IOAPIC/8259 */
-/* Global ACPI memory region. This region is used for passing information
+/*
+ * Global ACPI memory region. This region is used for passing information
* between coreboot (aka "the system bios"), ACPI, and the SMI handler.
* Since we don't know where this will end up in memory at ACPI compile time,
* we have to fix it up in coreboot's ACPI creation phase.
*/
+External (NVSA)
-External(NVSA)
OperationRegion (GNVS, SystemMemory, NVSA, 0x2000)
Field (GNVS, ByteAcc, NoLock, Preserve)
{
/* Miscellaneous */
Offset (0x00),
- OSYS, 16, // 0x00 - Operating System
- SMIF, 8, // 0x02 - SMI function
- PRM0, 8, // 0x03 - SMI function parameter
- PRM1, 8, // 0x04 - SMI function parameter
- SCIF, 8, // 0x05 - SCI function
- PRM2, 8, // 0x06 - SCI function parameter
- PRM3, 8, // 0x07 - SCI function parameter
- LCKF, 8, // 0x08 - Global Lock function for EC
- PRM4, 8, // 0x09 - Lock function parameter
- PRM5, 8, // 0x0a - Lock function parameter
- P80D, 32, // 0x0b - Debug port (IO 0x80) value
- LIDS, 8, // 0x0f - LID state (open = 1)
- PWRS, 8, // 0x10 - Power State (AC = 1)
- PCNT, 8, // 0x11 - Processor count
- TPMP, 8, // 0x12 - TPM Present and Enabled
- TLVL, 8, // 0x13 - Throttle Level
- PPCM, 8, // 0x14 - Maximum P-state usable by OS
- PM1I, 32, // 0x15 - System Wake Source - PM1 Index
+ OSYS, 16, /* 0x00 - Operating System */
+ SMIF, 8, /* 0x02 - SMI function */
+ PRM0, 8, /* 0x03 - SMI function parameter */
+ PRM1, 8, /* 0x04 - SMI function parameter */
+ SCIF, 8, /* 0x05 - SCI function */
+ PRM2, 8, /* 0x06 - SCI function parameter */
+ PRM3, 8, /* 0x07 - SCI function parameter */
+ LCKF, 8, /* 0x08 - Global Lock function for EC */
+ PRM4, 8, /* 0x09 - Lock function parameter */
+ PRM5, 8, /* 0x0a - Lock function parameter */
+ P80D, 32, /* 0x0b - Debug port (IO 0x80) value */
+ LIDS, 8, /* 0x0f - LID state (open = 1) */
+ PWRS, 8, /* 0x10 - Power State (AC = 1) */
+ PCNT, 8, /* 0x11 - Processor count */
+ TPMP, 8, /* 0x12 - TPM Present and Enabled */
+ TLVL, 8, /* 0x13 - Throttle Level */
+ PPCM, 8, /* 0x14 - Maximum P-state usable by OS */
+ PM1I, 32, /* 0x15 - System Wake Source - PM1 Index */
/* Device Config */
Offset (0x20),
- S5U0, 8, // 0x20 - Enable USB0 in S5
- S5U1, 8, // 0x21 - Enable USB1 in S5
- S3U0, 8, // 0x22 - Enable USB0 in S3
- S3U1, 8, // 0x23 - Enable USB1 in S3
- TACT, 8, // 0x24 - Thermal Active trip point
- TPSV, 8, // 0x25 - Thermal Passive trip point
- TCRT, 8, // 0x26 - Thermal Critical trip point
- DPTE, 8, // 0x27 - Enable DPTF
+ S5U0, 8, /* 0x20 - Enable USB0 in S5 */
+ S5U1, 8, /* 0x21 - Enable USB1 in S5 */
+ S3U0, 8, /* 0x22 - Enable USB0 in S3 */
+ S3U1, 8, /* 0x23 - Enable USB1 in S3 */
+ TACT, 8, /* 0x24 - Thermal Active trip point */
+ TPSV, 8, /* 0x25 - Thermal Passive trip point */
+ TCRT, 8, /* 0x26 - Thermal Critical trip point */
+ DPTE, 8, /* 0x27 - Enable DPTF */
/* Base addresses */
Offset (0x30),
- CMEM, 32, // 0x30 - CBMEM TOC
- TOLM, 32, // 0x34 - Top of Low Memory
- CBMC, 32, // 0x38 - coreboot mem console pointer
+ CMEM, 32, /* 0x30 - CBMEM TOC */
+ TOLM, 32, /* 0x34 - Top of Low Memory */
+ CBMC, 32, /* 0x38 - coreboot mem console pointer */
/* ChromeOS specific */
Offset (0x100),
diff --git a/src/soc/intel/baytrail/acpi/irqlinks.asl b/src/soc/intel/baytrail/acpi/irqlinks.asl
index 527aa58..ef3bdd4 100644
--- a/src/soc/intel/baytrail/acpi/irqlinks.asl
+++ b/src/soc/intel/baytrail/acpi/irqlinks.asl
@@ -5,20 +5,20 @@
Name (_HID, EISAID("PNP0C0F"))
Name (_UID, 1)
- // Disable method
+ /* Disable method */
Method (_DIS, 0, Serialized)
{
Store (0x80, PRTA)
}
- // Possible Resource Settings for this Link
+ /* Possible Resource Settings for this Link */
Name (_PRS, ResourceTemplate()
{
IRQ(Level, ActiveLow, Shared)
{ 3, 4, 5, 6, 7, 10, 12, 14, 15 }
})
- // Current Resource Settings for this link
+ /* Current Resource Settings for this link */
Method (_CRS, 0, Serialized)
{
Name (RTLA, ResourceTemplate()
@@ -27,28 +27,28 @@
})
CreateWordField(RTLA, 1, IRQ0)
- // Clear the WordField
+ /* Clear the WordField */
Store (Zero, IRQ0)
- // Set the bit from PRTA
+ /* Set the bit from PRTA */
ShiftLeft(1, And(PRTA, 0x0f), IRQ0)
Return (RTLA)
}
- // Set Resource Setting for this IRQ link
+ /* Set Resource Setting for this IRQ link */
Method (_SRS, 1, Serialized)
{
CreateWordField(Arg0, 1, IRQ0)
- // Which bit is set?
+ /* Which bit is set? */
FindSetRightBit(IRQ0, Local0)
Decrement(Local0)
Store(Local0, PRTA)
}
- // Status
+ /* Status */
Method (_STA, 0, Serialized)
{
If(And(PRTA, 0x80)) {
@@ -64,20 +64,20 @@
Name (_HID, EISAID("PNP0C0F"))
Name (_UID, 2)
- // Disable method
+ /* Disable method */
Method (_DIS, 0, Serialized)
{
Store (0x80, PRTB)
}
- // Possible Resource Settings for this Link
+ /* Possible Resource Settings for this Link */
Name (_PRS, ResourceTemplate()
{
IRQ(Level, ActiveLow, Shared)
{ 3, 4, 5, 6, 7, 11, 12, 14, 15 }
})
- // Current Resource Settings for this link
+ /* Current Resource Settings for this link */
Method (_CRS, 0, Serialized)
{
Name (RTLB, ResourceTemplate()
@@ -86,28 +86,28 @@
})
CreateWordField(RTLB, 1, IRQ0)
- // Clear the WordField
+ /* Clear the WordField */
Store (Zero, IRQ0)
- // Set the bit from PRTB
+ /* Set the bit from PRTB */
ShiftLeft(1, And(PRTB, 0x0f), IRQ0)
Return (RTLB)
}
- // Set Resource Setting for this IRQ link
+ /* Set Resource Setting for this IRQ link */
Method (_SRS, 1, Serialized)
{
CreateWordField(Arg0, 1, IRQ0)
- // Which bit is set?
+ /* Which bit is set? */
FindSetRightBit(IRQ0, Local0)
Decrement(Local0)
Store(Local0, PRTB)
}
- // Status
+ /* Status */
Method (_STA, 0, Serialized)
{
If(And(PRTB, 0x80)) {
@@ -123,20 +123,20 @@
Name (_HID, EISAID("PNP0C0F"))
Name (_UID, 3)
- // Disable method
+ /* Disable method */
Method (_DIS, 0, Serialized)
{
Store (0x80, PRTC)
}
- // Possible Resource Settings for this Link
+ /* Possible Resource Settings for this Link */
Name (_PRS, ResourceTemplate()
{
IRQ(Level, ActiveLow, Shared)
{ 3, 4, 5, 6, 7, 10, 12, 14, 15 }
})
- // Current Resource Settings for this link
+ /* Current Resource Settings for this link */
Method (_CRS, 0, Serialized)
{
Name (RTLC, ResourceTemplate()
@@ -145,28 +145,28 @@
})
CreateWordField(RTLC, 1, IRQ0)
- // Clear the WordField
+ /* Clear the WordField */
Store (Zero, IRQ0)
- // Set the bit from PRTC
+ /* Set the bit from PRTC */
ShiftLeft(1, And(PRTC, 0x0f), IRQ0)
Return (RTLC)
}
- // Set Resource Setting for this IRQ link
+ /* Set Resource Setting for this IRQ link */
Method (_SRS, 1, Serialized)
{
CreateWordField(Arg0, 1, IRQ0)
- // Which bit is set?
+ /* Which bit is set? */
FindSetRightBit(IRQ0, Local0)
Decrement(Local0)
Store(Local0, PRTC)
}
- // Status
+ /* Status */
Method (_STA, 0, Serialized)
{
If(And(PRTC, 0x80)) {
@@ -182,20 +182,20 @@
Name (_HID, EISAID("PNP0C0F"))
Name (_UID, 4)
- // Disable method
+ /* Disable method */
Method (_DIS, 0, Serialized)
{
Store (0x80, PRTD)
}
- // Possible Resource Settings for this Link
+ /* Possible Resource Settings for this Link */
Name (_PRS, ResourceTemplate()
{
IRQ(Level, ActiveLow, Shared)
{ 3, 4, 5, 6, 7, 11, 12, 14, 15 }
})
- // Current Resource Settings for this link
+ /* Current Resource Settings for this link */
Method (_CRS, 0, Serialized)
{
Name (RTLD, ResourceTemplate()
@@ -204,28 +204,28 @@
})
CreateWordField(RTLD, 1, IRQ0)
- // Clear the WordField
+ /* Clear the WordField */
Store (Zero, IRQ0)
- // Set the bit from PRTD
+ /* Set the bit from PRTD */
ShiftLeft(1, And(PRTD, 0x0f), IRQ0)
Return (RTLD)
}
- // Set Resource Setting for this IRQ link
+ /* Set Resource Setting for this IRQ link */
Method (_SRS, 1, Serialized)
{
CreateWordField(Arg0, 1, IRQ0)
- // Which bit is set?
+ /* Which bit is set? */
FindSetRightBit(IRQ0, Local0)
Decrement(Local0)
Store(Local0, PRTD)
}
- // Status
+ /* Status */
Method (_STA, 0, Serialized)
{
If(And(PRTD, 0x80)) {
@@ -241,20 +241,20 @@
Name (_HID, EISAID("PNP0C0F"))
Name (_UID, 5)
- // Disable method
+ /* Disable method */
Method (_DIS, 0, Serialized)
{
Store (0x80, PRTE)
}
- // Possible Resource Settings for this Link
+ /* Possible Resource Settings for this Link */
Name (_PRS, ResourceTemplate()
{
IRQ(Level, ActiveLow, Shared)
{ 3, 4, 5, 6, 7, 10, 12, 14, 15 }
})
- // Current Resource Settings for this link
+ /* Current Resource Settings for this link */
Method (_CRS, 0, Serialized)
{
Name (RTLE, ResourceTemplate()
@@ -263,28 +263,28 @@
})
CreateWordField(RTLE, 1, IRQ0)
- // Clear the WordField
+ /* Clear the WordField */
Store (Zero, IRQ0)
- // Set the bit from PRTE
+ /* Set the bit from PRTE */
ShiftLeft(1, And(PRTE, 0x0f), IRQ0)
Return (RTLE)
}
- // Set Resource Setting for this IRQ link
+ /* Set Resource Setting for this IRQ link */
Method (_SRS, 1, Serialized)
{
CreateWordField(Arg0, 1, IRQ0)
- // Which bit is set?
+ /* Which bit is set? */
FindSetRightBit(IRQ0, Local0)
Decrement(Local0)
Store(Local0, PRTE)
}
- // Status
+ /* Status */
Method (_STA, 0, Serialized)
{
If(And(PRTE, 0x80)) {
@@ -300,20 +300,20 @@
Name (_HID, EISAID("PNP0C0F"))
Name (_UID, 6)
- // Disable method
+ /* Disable method */
Method (_DIS, 0, Serialized)
{
Store (0x80, PRTF)
}
- // Possible Resource Settings for this Link
+ /* Possible Resource Settings for this Link */
Name (_PRS, ResourceTemplate()
{
IRQ(Level, ActiveLow, Shared)
{ 3, 4, 5, 6, 7, 11, 12, 14, 15 }
})
- // Current Resource Settings for this link
+ /* Current Resource Settings for this link */
Method (_CRS, 0, Serialized)
{
Name (RTLF, ResourceTemplate()
@@ -322,28 +322,28 @@
})
CreateWordField(RTLF, 1, IRQ0)
- // Clear the WordField
+ /* Clear the WordField */
Store (Zero, IRQ0)
- // Set the bit from PRTF
+ /* Set the bit from PRTF */
ShiftLeft(1, And(PRTF, 0x0f), IRQ0)
Return (RTLF)
}
- // Set Resource Setting for this IRQ link
+ /* Set Resource Setting for this IRQ link */
Method (_SRS, 1, Serialized)
{
CreateWordField(Arg0, 1, IRQ0)
- // Which bit is set?
+ /* Which bit is set? */
FindSetRightBit(IRQ0, Local0)
Decrement(Local0)
Store(Local0, PRTF)
}
- // Status
+ /* Status */
Method (_STA, 0, Serialized)
{
If(And(PRTF, 0x80)) {
@@ -359,20 +359,20 @@
Name (_HID, EISAID("PNP0C0F"))
Name (_UID, 7)
- // Disable method
+ /* Disable method */
Method (_DIS, 0, Serialized)
{
Store (0x80, PRTG)
}
- // Possible Resource Settings for this Link
+ /* Possible Resource Settings for this Link */
Name (_PRS, ResourceTemplate()
{
IRQ(Level, ActiveLow, Shared)
{ 3, 4, 5, 6, 7, 10, 12, 14, 15 }
})
- // Current Resource Settings for this link
+ /* Current Resource Settings for this link */
Method (_CRS, 0, Serialized)
{
Name (RTLG, ResourceTemplate()
@@ -381,28 +381,28 @@
})
CreateWordField(RTLG, 1, IRQ0)
- // Clear the WordField
+ /* Clear the WordField */
Store (Zero, IRQ0)
- // Set the bit from PRTG
+ /* Set the bit from PRTG */
ShiftLeft(1, And(PRTG, 0x0f), IRQ0)
Return (RTLG)
}
- // Set Resource Setting for this IRQ link
+ /* Set Resource Setting for this IRQ link */
Method (_SRS, 1, Serialized)
{
CreateWordField(Arg0, 1, IRQ0)
- // Which bit is set?
+ /* Which bit is set? */
FindSetRightBit(IRQ0, Local0)
Decrement(Local0)
Store(Local0, PRTG)
}
- // Status
+ /* Status */
Method (_STA, 0, Serialized)
{
If(And(PRTG, 0x80)) {
@@ -418,20 +418,20 @@
Name (_HID, EISAID("PNP0C0F"))
Name (_UID, 8)
- // Disable method
+ /* Disable method */
Method (_DIS, 0, Serialized)
{
Store (0x80, PRTH)
}
- // Possible Resource Settings for this Link
+ /* Possible Resource Settings for this Link */
Name (_PRS, ResourceTemplate()
{
IRQ(Level, ActiveLow, Shared)
{ 3, 4, 5, 6, 7, 11, 12, 14, 15 }
})
- // Current Resource Settings for this link
+ /* Current Resource Settings for this link */
Method (_CRS, 0, Serialized)
{
Name (RTLH, ResourceTemplate()
@@ -440,28 +440,28 @@
})
CreateWordField(RTLH, 1, IRQ0)
- // Clear the WordField
+ /* Clear the WordField */
Store (Zero, IRQ0)
- // Set the bit from PRTH
+ /* Set the bit from PRTH */
ShiftLeft(1, And(PRTH, 0x0f), IRQ0)
Return (RTLH)
}
- // Set Resource Setting for this IRQ link
+ /* Set Resource Setting for this IRQ link */
Method (_SRS, 1, Serialized)
{
CreateWordField(Arg0, 1, IRQ0)
- // Which bit is set?
+ /* Which bit is set? */
FindSetRightBit(IRQ0, Local0)
Decrement(Local0)
Store(Local0, PRTH)
}
- // Status
+ /* Status */
Method (_STA, 0, Serialized)
{
If(And(PRTH, 0x80)) {
diff --git a/src/soc/intel/baytrail/acpi/irqroute.asl b/src/soc/intel/baytrail/acpi/irqroute.asl
index 69c7856..41c660f 100644
--- a/src/soc/intel/baytrail/acpi/irqroute.asl
+++ b/src/soc/intel/baytrail/acpi/irqroute.asl
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-// PCI Interrupt Routing
+/* PCI Interrupt Routing */
Method(_PRT)
{
If (PICM) {
diff --git a/src/soc/intel/baytrail/acpi/lpc.asl b/src/soc/intel/baytrail/acpi/lpc.asl
index 02e1085..9b07ab8 100644
--- a/src/soc/intel/baytrail/acpi/lpc.asl
+++ b/src/soc/intel/baytrail/acpi/lpc.asl
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-// Intel LPC Bus Device - 0:1f.0
+/* Intel LPC Bus Device - 0:1f.0 */
Device (LPCB)
{
@@ -10,7 +10,7 @@
#include "acpi/ec.asl"
- Device (DMAC) // DMA Controller
+ Device (DMAC) /* DMA Controller */
{
Name(_HID, EISAID("PNP0200"))
Name(_CRS, ResourceTemplate()
@@ -23,7 +23,7 @@
})
}
- Device (FWH) // Firmware Hub
+ Device (FWH) /* Firmware Hub */
{
Name (_HID, EISAID("INT0800"))
Name (_CRS, ResourceTemplate()
@@ -37,9 +37,9 @@
Name (_HID, EISAID("PNP0103"))
Name (_CID, 0x010CD041)
- Method (_STA, 0) // Device Status
+ Method (_STA, 0) /* Device Status */
{
- Return (0xf) // Enable and show device
+ Return (0xf) /* Enable and show device */
}
Name(_CRS, ResourceTemplate()
@@ -48,7 +48,7 @@
})
}
- Device(PIC) // 8259 Interrupt Controller
+ Device(PIC) /* 8259 Interrupt Controller */
{
Name(_HID,EISAID("PNP0000"))
Name(_CRS, ResourceTemplate()
@@ -74,20 +74,20 @@
})
}
- Device(LDRC) // LPC device: Resource consumption
+ Device(LDRC) /* LPC device: Resource consumption */
{
Name (_HID, EISAID("PNP0C02"))
Name (_UID, 2)
Name (RBUF, ResourceTemplate()
{
- IO (Decode16, 0x61, 0x61, 0x1, 0x01) // NMI Status
- IO (Decode16, 0x63, 0x63, 0x1, 0x01) // CPU Reserved
- IO (Decode16, 0x65, 0x65, 0x1, 0x01) // CPU Reserved
- IO (Decode16, 0x67, 0x67, 0x1, 0x01) // CPU Reserved
- IO (Decode16, 0x80, 0x80, 0x1, 0x01) // Port 80 Post
- IO (Decode16, 0x92, 0x92, 0x1, 0x01) // CPU Reserved
- IO (Decode16, 0xb2, 0xb2, 0x1, 0x02) // SWSMI
+ IO (Decode16, 0x61, 0x61, 0x1, 0x01) /* NMI Status */
+ IO (Decode16, 0x63, 0x63, 0x1, 0x01) /* CPU Reserved */
+ IO (Decode16, 0x65, 0x65, 0x1, 0x01) /* CPU Reserved */
+ IO (Decode16, 0x67, 0x67, 0x1, 0x01) /* CPU Reserved */
+ IO (Decode16, 0x80, 0x80, 0x1, 0x01) /* Port 80 Post */
+ IO (Decode16, 0x92, 0x92, 0x1, 0x01) /* CPU Reserved */
+ IO (Decode16, 0xb2, 0xb2, 0x1, 0x02) /* SWSMI */
})
Method (_CRS, 0, NotSerialized)
@@ -96,18 +96,20 @@
}
}
- Device (RTC) // Real Time Clock
+ Device (RTC) /* Real Time Clock */
{
Name (_HID, EISAID("PNP0B00"))
Name (_CRS, ResourceTemplate()
{
IO (Decode16, 0x70, 0x70, 1, 8)
-// Disable as Windows doesn't like it, and systems don't seem to use it.
-// IRQNoFlags() { 8 }
+/*
+ * Disable as Windows doesn't like it, and systems don't seem to use it.
+ * IRQNoFlags() { 8 }
+ */
})
}
- Device (TIMR) // Intel 8254 timer
+ Device (TIMR) /* Intel 8254 timer */
{
Name(_HID, EISAID("PNP0100"))
Name(_CRS, ResourceTemplate()
@@ -118,6 +120,6 @@
})
}
- // Include mainboard's superio.asl file.
+ /* Include mainboard's superio.asl file. */
#include "acpi/superio.asl"
}
diff --git a/src/soc/intel/baytrail/acpi/platform.asl b/src/soc/intel/baytrail/acpi/platform.asl
index 4991e36..67b515a 100644
--- a/src/soc/intel/baytrail/acpi/platform.asl
+++ b/src/soc/intel/baytrail/acpi/platform.asl
@@ -2,7 +2,8 @@
#include <southbridge/intel/common/acpi/platform.asl>
-/* The _PTS method (Prepare To Sleep) is called before the OS is
+/*
+ * The _PTS method (Prepare To Sleep) is called before the OS is
* entering a sleep state. The sleep state number is passed in Arg0
*/
diff --git a/src/soc/intel/baytrail/acpi/southcluster.asl b/src/soc/intel/baytrail/acpi/southcluster.asl
index 9c5fa1a..e3997d7 100644
--- a/src/soc/intel/baytrail/acpi/southcluster.asl
+++ b/src/soc/intel/baytrail/acpi/southcluster.asl
@@ -5,16 +5,16 @@
Scope(\)
{
- // IO-Trap at 0x800. This is the ACPI->SMI communication interface.
+ /* IO-Trap at 0x800. This is the ACPI->SMI communication interface. */
OperationRegion(IO_T, SystemIO, 0x800, 0x10)
Field(IO_T, ByteAcc, NoLock, Preserve)
{
Offset(0x8),
- TRP0, 8 // IO-Trap at 0x808
+ TRP0, 8 /* IO-Trap at 0x808 */
}
- // Intel Legacy Block
+ /* Intel Legacy Block */
OperationRegion(ILBS, SystemMemory, ILB_BASE_ADDRESS, ILB_BASE_SIZE)
Field (ILBS, AnyAcc, NoLock, Preserve)
{
@@ -30,8 +30,8 @@
}
}
-Name(_HID,EISAID("PNP0A08")) // PCIe
-Name(_CID,EISAID("PNP0A03")) // PCI
+Name(_HID,EISAID("PNP0A08")) /* PCIe */
+Name(_CID,EISAID("PNP0A03")) /* PCI */
Name(_BBN, 0)
@@ -152,12 +152,12 @@
Method (_CRS, 0, Serialized)
{
- // Update PCI resource area
+ /* Update PCI resource area */
CreateDwordField(MCRS, ^PMEM._MIN, PMIN)
CreateDwordField(MCRS, ^PMEM._MAX, PMAX)
CreateDwordField(MCRS, ^PMEM._LEN, PLEN)
- // TOLM is BMBOUND accessible from IOSF so is saved in NVS
+ /* TOLM is BMBOUND accessible from IOSF so is saved in NVS */
Store (\TOLM, PMIN)
Store (Subtract(CONFIG_MMCONF_BASE_ADDRESS, 1), PMAX)
Add (Subtract (PMAX, PMIN), 1, PLEN)
@@ -182,7 +182,7 @@
Memory32Fixed(ReadWrite, RCBA_BASE_ADDRESS, RCBA_BASE_SIZE)
})
- // Current Resource Settings
+ /* Current Resource Settings */
Method (_CRS, 0, Serialized)
{
Return(PDRS)
@@ -227,13 +227,13 @@
}
}
-// LPC Bridge 0:1f.0
+/* LPC Bridge 0:1f.0 */
#include "lpc.asl"
-// USB XHCI 0:14.0
+/* USB XHCI 0:14.0 */
#include "xhci.asl"
-// IRQ routing for each PCI device
+/* IRQ routing for each PCI device */
#include "irqroute.asl"
// PCI Express Ports 0:1c.x
@@ -241,16 +241,16 @@
Scope (\_SB)
{
- // GPIO Devices
+ /* GPIO Devices */
#include "gpio.asl"
}
Scope (\_SB.PCI0)
{
- // LPSS Devices
+ /* LPSS Devices */
#include "lpss.asl"
- // SCC Devices
+ /* SCC Devices */
#include "scc.asl"
// LPE Device
diff --git a/src/soc/intel/baytrail/bootblock/bootblock.c b/src/soc/intel/baytrail/bootblock/bootblock.c
index 54e7261..0f3980c 100644
--- a/src/soc/intel/baytrail/bootblock/bootblock.c
+++ b/src/soc/intel/baytrail/bootblock/bootblock.c
@@ -13,10 +13,11 @@
{
uint32_t reg;
- /* Set up the MMCONF range. The register lives in the BUNIT. The
- * IO variant of the config access needs to be used initially to
- * properly configure as the IOSF access registers live in PCI
- * config space. */
+ /*
+ * Set up the MMCONF range. The register lives in the BUNIT. The IO variant of the
+ * config access needs to be used initially to properly configure as the IOSF access
+ * registers live in PCI config space.
+ */
reg = 0;
/* Clear the extended register. */
pci_io_write_config32(IOSF_PCI_DEV, MCRX_REG, reg);
@@ -98,11 +99,11 @@
just pick the one that is called first. */
void bootblock_early_northbridge_init(void)
{
- /* Allow memory-mapped PCI config access. */
+ /* Allow memory-mapped PCI config access */
setup_mmconfig();
+ /* Early chipset initialization */
program_base_addresses();
-
tco_disable();
if (CONFIG(ENABLE_BUILTIN_COM1))
diff --git a/src/soc/intel/baytrail/cpu.c b/src/soc/intel/baytrail/cpu.c
index 5900261..b1cb8d5 100644
--- a/src/soc/intel/baytrail/cpu.c
+++ b/src/soc/intel/baytrail/cpu.c
@@ -35,10 +35,11 @@
{
printk(BIOS_DEBUG, "Init BayTrail core.\n");
- /* On bay trail the turbo disable bit is actually scoped at building
- * block level -- not package. For non-bsp cores that are within a
- * building block enable turbo. The cores within the BSP's building
- * block will just see it already enabled and move on. */
+ /*
+ * The turbo disable bit is actually scoped at building block level -- not package.
+ * For non-BSP cores that are within a building block, enable turbo. The cores within
+ * the BSP's building block will just see it already enabled and move on.
+ */
if (lapicid())
enable_turbo();
@@ -95,9 +96,8 @@
x86_mtrr_check();
/*
- * Configure the BUNIT to allow dirty cache line evictions in non-SMM
- * mode for the lines that were dirtied while in SMM mode. Otherwise
- * the writes would be silently dropped.
+ * Configure the BUNIT to allow dirty cache line evictions in non-SMM mode for lines
+ * that were dirtied while in SMM mode. Otherwise the writes would be silently dropped.
*/
bsmrwac = iosf_bunit_read(BUNIT_SMRWAC) | SAI_IA_UNTRUSTED;
iosf_bunit_write(BUNIT_SMRWAC, bsmrwac);
diff --git a/src/soc/intel/baytrail/include/soc/device_nvs.h b/src/soc/intel/baytrail/include/soc/device_nvs.h
index b2f3bd2..6a5f108 100644
--- a/src/soc/intel/baytrail/include/soc/device_nvs.h
+++ b/src/soc/intel/baytrail/include/soc/device_nvs.h
@@ -35,7 +35,7 @@
u32 scc_bar0[3];
u32 lpe_bar0;
- /* BAR 0 */
+ /* BAR 1 */
u32 lpss_bar1[14];
u32 scc_bar1[3];
u32 lpe_bar1;
diff --git a/src/soc/intel/baytrail/include/soc/iosf.h b/src/soc/intel/baytrail/include/soc/iosf.h
index 1d105a2..15d77de 100644
--- a/src/soc/intel/baytrail/include/soc/iosf.h
+++ b/src/soc/intel/baytrail/include/soc/iosf.h
@@ -12,17 +12,17 @@
* MCR - control register
* MDR - data register
* MCRX - control register extension
- * The extension regist is only used for addresses that don't fit into the
- * 8 bit register address.
+ * The extension register is only used for addresses that don't fit
+ * into the 8 bit register address.
*/
#ifndef PCI_DEV
#define PCI_DEV(SEGBUS, DEV, FN) ( \
- (((SEGBUS) & 0xFFF) << 20) | \
- (((DEV) & 0x1F) << 15) | \
- (((FN) & 0x07) << 12))
+ (((SEGBUS) & 0xFFF) << 20) | \
+ (((DEV) & 0x1F) << 15) | \
+ (((FN) & 0x07) << 12))
#endif
-#define IOSF_PCI_DEV PCI_DEV(0,SOC_DEV,SOC_FUNC)
+#define IOSF_PCI_DEV PCI_DEV(0, SOC_DEV, SOC_FUNC)
#define MCR_REG 0xd0
#define IOSF_OPCODE(x) ((x) << 24)
diff --git a/src/soc/intel/baytrail/include/soc/irq.h b/src/soc/intel/baytrail/include/soc/irq.h
index ca4cac1..967bc35 100644
--- a/src/soc/intel/baytrail/include/soc/irq.h
+++ b/src/soc/intel/baytrail/include/soc/irq.h
@@ -11,6 +11,7 @@
#define PIRQF_APIC_IRQ 21
#define PIRQG_APIC_IRQ 22
#define PIRQH_APIC_IRQ 23
+
/* The below IRQs are for when devices are in ACPI mode. Active low. */
#define LPE_DMA0_IRQ 24
#define LPE_DMA1_IRQ 25
@@ -110,9 +111,11 @@
# define SCIS_IRQ22 0x06
# define SCIS_IRQ23 0x07
-/* In each mainboard directory there should exist a header file irqroute.h that
+/*
+ * In each mainboard directory there should exist a header file irqroute.h that
* defines the PCI_DEV_PIRQ_ROUTES and PIRQ_PIC_ROUTES macros which
- * consist of PCI_DEV_PIRQ_ROUTE and PIRQ_PIC entries. */
+ * consist of PCI_DEV_PIRQ_ROUTE and PIRQ_PIC entries.
+ */
#if !defined(__ASSEMBLER__) && !defined(__ACPI__)
#include <stdint.h>
@@ -135,9 +138,10 @@
.pic = { PIRQ_PIC_ROUTES, }, \
}
+/* The following macros are used for ACPI by the ASL compiler */
#define PCI_DEV_PIRQ_ROUTE(dev_, a_, b_, c_, d_) \
[dev_] = ((PIRQ ## d_) << 12) | ((PIRQ ## c_) << 8) | \
- ((PIRQ ## b_) << 4) | ((PIRQ ## a_) << 0)
+ ((PIRQ ## b_) << 4) | ((PIRQ ## a_) << 0)
#define PIRQ_PIC(pirq_, pic_irq_) \
[PIRQ ## pirq_] = PIRQ_PIC_IRQ ## pic_irq_
diff --git a/src/soc/intel/baytrail/include/soc/nvs.h b/src/soc/intel/baytrail/include/soc/nvs.h
index cdffc75..41b827e 100644
--- a/src/soc/intel/baytrail/include/soc/nvs.h
+++ b/src/soc/intel/baytrail/include/soc/nvs.h
@@ -48,7 +48,7 @@
u8 unused[76];
- /* ChromeOS specific (0x100-0xfff)*/
+ /* ChromeOS specific (0x100-0xfff) */
chromeos_acpi_t chromeos;
/* Baytrail LPSS (0x1000) */
diff --git a/src/soc/intel/baytrail/include/soc/pattrs.h b/src/soc/intel/baytrail/include/soc/pattrs.h
index c1ca7f4..d485484 100644
--- a/src/soc/intel/baytrail/include/soc/pattrs.h
+++ b/src/soc/intel/baytrail/include/soc/pattrs.h
@@ -14,7 +14,8 @@
IACORE_END
};
-/* The pattrs structure is a common place to stash pertinent information
+/*
+ * The pattrs structure is a common place to stash pertinent information
* about the processor or platform. Instead of going to the source (msrs, cpuid)
* every time an attribute is needed use the pattrs structure.
*/
@@ -32,8 +33,10 @@
unsigned int bclk_khz;
};
-/* This is just to hide the abstraction w/o relying on how the underlying
- * storage is allocated. */
+/*
+ * This is just to hide the abstraction w/o relying on how the underlying
+ * storage is allocated.
+ */
#define PATTRS_GLOB_NAME __global_pattrs
#define DEFINE_PATTRS struct pattrs PATTRS_GLOB_NAME
extern DEFINE_PATTRS;
@@ -43,5 +46,4 @@
return &PATTRS_GLOB_NAME;
}
-
#endif /* _PATTRS_H_ */
diff --git a/src/soc/intel/baytrail/include/soc/pm.h b/src/soc/intel/baytrail/include/soc/pm.h
index 0481159..5886fe5 100644
--- a/src/soc/intel/baytrail/include/soc/pm.h
+++ b/src/soc/intel/baytrail/include/soc/pm.h
@@ -204,21 +204,21 @@
#define _ACPI_ENABLE_WAKE_SUS_GPIO(x) SUS_GPIO_EN##x##_BIT
#define ACPI_ENABLE_WAKE_SUS_GPIO(x) _ACPI_ENABLE_WAKE_SUS_GPIO(x)
#define SMI_EN 0x30
-#define INTEL_USB2_EN (1 << 18) // Intel-Specific USB2 SMI logic
-#define USB_EN (1 << 17) // Legacy USB2 SMI logic
-#define PERIODIC_EN (1 << 14) // SMI on PERIODIC_STS in SMI_STS
-#define TCO_EN (1 << 13) // Enable TCO Logic (BIOSWE et al)
-#define BIOS_RLS (1 << 7) // asserts SCI on bit set
-#define SWSMI_TMR_EN (1 << 6) // start software smi timer on bit set
-#define APMC_EN (1 << 5) // Writes to APM_CNT cause SMI#
-#define SLP_SMI_EN (1 << 4) // Write to SLP_EN in PM1_CNT asserts SMI#
-#define BIOS_EN (1 << 2) // Assert SMI# on setting GBL_RLS bit
-#define EOS (1 << 1) // End of SMI (deassert SMI#)
-#define GBL_SMI_EN (1 << 0) // SMI# generation at all?
+#define INTEL_USB2_EN (1 << 18) /* Intel-Specific USB2 SMI logic */
+#define USB_EN (1 << 17) /* Legacy USB2 SMI logic */
+#define PERIODIC_EN (1 << 14) /* SMI on PERIODIC_STS in SMI_STS */
+#define TCO_EN (1 << 13) /* Enable TCO Logic (BIOSWE et al) */
+#define BIOS_RLS (1 << 7) /* asserts SCI on bit set */
+#define SWSMI_TMR_EN (1 << 6) /* start software smi timer on bit set */
+#define APMC_EN (1 << 5) /* Writes to APM_CNT cause SMI# */
+#define SLP_SMI_EN (1 << 4) /* Write to SLP_EN in PM1_CNT asserts SMI# */
+#define BIOS_EN (1 << 2) /* Assert SMI# on setting GBL_RLS bit */
+#define EOS (1 << 1) /* End of SMI (deassert SMI#) */
+#define GBL_SMI_EN (1 << 0) /* SMI# generation at all? */
#define SMI_STS 0x34
#define ALT_GPIO_SMI 0x38
#define UPRWC 0x3c
-# define UPRWC_WR_EN (1 << 1) // USB Per-Port Registers Write Enable
+# define UPRWC_WR_EN (1 << 1) /* USB Per-Port Registers Write Enable */
#define GPE_CTRL 0x40
#define PM2A_CNT_BLK 0x50
#define TCO_RLD 0x60
diff --git a/src/soc/intel/baytrail/lpe.c b/src/soc/intel/baytrail/lpe.c
index c41db94..e31e15e 100644
--- a/src/soc/intel/baytrail/lpe.c
+++ b/src/soc/intel/baytrail/lpe.c
@@ -19,9 +19,10 @@
#include <soc/ramstage.h>
#include "chip.h"
-
-/* The LPE audio devices needs 1MiB of memory reserved aligned to a 512MiB
- * address. Just take 1MiB @ 512MiB. */
+/*
+ * The LPE audio devices needs 1MiB of memory reserved aligned to a 512MiB
+ * address. Just take 1MiB @ 512MiB.
+ */
#define FIRMWARE_PHYS_BASE (512 << 20)
#define FIRMWARE_PHYS_LENGTH (1 << 20)
#define FIRMWARE_PCI_REG_BASE 0xa8
@@ -82,10 +83,12 @@
freq_str = "19.2";
reg = CLK_FREQ_19P2MHZ;
break;
+
case 25:
freq_str = "25";
reg = CLK_FREQ_25MHZ;
break;
+
default:
printk(BIOS_DEBUG, "LPE codec clock not required.\n");
return;
@@ -138,7 +141,6 @@
struct soc_intel_baytrail_config *config = config_of(dev);
lpe_stash_firmware_info(dev);
-
setup_codec_clock(dev);
if (config->lpe_acpi_mode)
diff --git a/src/soc/intel/baytrail/northcluster.c b/src/soc/intel/baytrail/northcluster.c
index 32b1385..667c8e8 100644
--- a/src/soc/intel/baytrail/northcluster.c
+++ b/src/soc/intel/baytrail/northcluster.c
@@ -11,7 +11,8 @@
#include <soc/pci_devs.h>
#include <soc/ramstage.h>
-/* Host Memory Map:
+/*
+ * Host Memory Map:
*
* +--------------------------+ BMBOUND_HI
* | Usable DRAM |
diff --git a/src/soc/intel/baytrail/pmutil.c b/src/soc/intel/baytrail/pmutil.c
index 8addc53..6066be7 100644
--- a/src/soc/intel/baytrail/pmutil.c
+++ b/src/soc/intel/baytrail/pmutil.c
@@ -26,7 +26,8 @@
return pcu_dev;
}
-#else
+#else /* __SIMPLE_DEVICE__ */
+
static struct device *pcu_dev;
static struct device *get_pcu_dev(void)
{
@@ -34,7 +35,7 @@
pcu_dev = pcidev_on_root(PCU_DEV, 0);
return pcu_dev;
}
-#endif
+#endif /* __SIMPLE_DEVICE__ */
uint16_t get_pmbase(void)
{
@@ -363,7 +364,6 @@
gen_pmcon1 = read32((u32 *)(PMC_BASE_ADDRESS + GEN_PMCON1));
rtc_fail = !!(gen_pmcon1 & RPS);
-
if (rtc_fail)
printk(BIOS_DEBUG, "RTC failure.\n");
diff --git a/src/soc/intel/baytrail/smihandler.c b/src/soc/intel/baytrail/smihandler.c
index 42d63e8..57e8583 100644
--- a/src/soc/intel/baytrail/smihandler.c
+++ b/src/soc/intel/baytrail/smihandler.c
@@ -25,7 +25,8 @@
switch (smif) {
case 0x32:
printk(BIOS_DEBUG, "OS Init\n");
- /* gnvs->smif:
+ /*
+ * gnvs->smif:
* On success, the IO Trap Handler returns 0
* On failure, the IO Trap Handler returns a value != 0
*/
@@ -98,9 +99,7 @@
if (slp_typ >= ACPI_S3)
elog_gsmi_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ);
- /* Next, do the deed.
- */
-
+ /* Next, do the deed. */
switch (slp_typ) {
case ACPI_S0:
printk(BIOS_DEBUG, "SMI#: Entering S0 (On)\n");
@@ -123,7 +122,7 @@
/* Disable all GPE */
disable_all_gpe();
- /* also iterates over all bridges on bus 0 */
+ /* Also iterates over all bridges on bus 0 */
busmaster_disable_on_bus(0);
break;
default:
@@ -131,9 +130,9 @@
break;
}
- /* Write back to the SLP register to cause the originally intended
- * event again. We need to set BIT13 (SLP_EN) though to make the
- * sleep happen.
+ /*
+ * Write back to the SLP register to cause the originally intended event again.
+ * We need to set BIT13 (SLP_EN) though to make the sleep happen.
*/
enable_pm1_control(SLP_EN);
@@ -141,7 +140,8 @@
if (slp_typ >= ACPI_S3)
halt();
- /* In most sleep states, the code flow of this function ends at
+ /*
+ * In most sleep states, the code flow of this function ends at
* the line above. However, if we entered sleep state S1 and wake
* up again, we will continue to execute code in this function.
*/
@@ -153,9 +153,8 @@
}
/*
- * Look for Synchronous IO SMI and use save state from that
- * core in case we are not running on the same core that
- * initiated the IO transaction.
+ * Look for Synchronous IO SMI and use save state from that core in case
+ * we are not running on the same core that initiated the IO transaction.
*/
static em64t100_smm_state_save_area_t *smi_apmc_find_state_save(uint8_t cmd)
{
@@ -293,14 +292,16 @@
reg8 = inb(APM_CNT);
switch (reg8) {
case APM_CNT_CST_CONTROL:
- /* Calling this function seems to cause
+ /*
+ * Calling this function seems to cause
* some kind of race condition in Linux
* and causes a kernel oops
*/
printk(BIOS_DEBUG, "C-state control\n");
break;
case APM_CNT_PST_CONTROL:
- /* Calling this function seems to cause
+ /*
+ * Calling this function seems to cause
* some kind of race condition in Linux
* and causes a kernel oops
*/
@@ -348,11 +349,9 @@
{
uint16_t pm1_sts = clear_pm1_status();
- /* While OSPM is not active, poweroff immediately
- * on a power button event.
- */
+ /* While OSPM is not active, poweroff immediately on a power button event */
if (pm1_sts & PWRBTN_STS) {
- // power button pressed
+ /* Power button pressed */
elog_gsmi_add_event(ELOG_TYPE_POWER_BUTTON);
disable_pm1_control(-1UL);
enable_pm1_control(SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT));
@@ -394,38 +393,38 @@
typedef void (*smi_handler_t)(void);
static const smi_handler_t southbridge_smi[32] = {
- NULL, // [0] reserved
- NULL, // [1] reserved
- NULL, // [2] BIOS_STS
- NULL, // [3] LEGACY_USB_STS
- southbridge_smi_sleep, // [4] SLP_SMI_STS
- southbridge_smi_apmc, // [5] APM_STS
- NULL, // [6] SWSMI_TMR_STS
- NULL, // [7] reserved
- southbridge_smi_pm1, // [8] PM1_STS
- southbridge_smi_gpe0, // [9] GPE0_STS
- NULL, // [10] reserved
- NULL, // [11] reserved
- NULL, // [12] reserved
- southbridge_smi_tco, // [13] TCO_STS
- southbridge_smi_periodic, // [14] PERIODIC_STS
- NULL, // [15] SERIRQ_SMI_STS
- NULL, // [16] SMBUS_SMI_STS
- NULL, // [17] LEGACY_USB2_STS
- NULL, // [18] INTEL_USB2_STS
- NULL, // [19] reserved
- NULL, // [20] PCI_EXP_SMI_STS
- NULL, // [21] reserved
- NULL, // [22] reserved
- NULL, // [23] reserved
- NULL, // [24] reserved
- NULL, // [25] reserved
- NULL, // [26] SPI_STS
- NULL, // [27] reserved
- NULL, // [28] PUNIT
- NULL, // [29] GUNIT
- NULL, // [30] reserved
- NULL // [31] reserved
+ NULL, /* [0] reserved */
+ NULL, /* [1] reserved */
+ NULL, /* [2] BIOS_STS */
+ NULL, /* [3] LEGACY_USB_STS */
+ southbridge_smi_sleep, /* [4] SLP_SMI_STS */
+ southbridge_smi_apmc, /* [5] APM_STS */
+ NULL, /* [6] SWSMI_TMR_STS */
+ NULL, /* [7] reserved */
+ southbridge_smi_pm1, /* [8] PM1_STS */
+ southbridge_smi_gpe0, /* [9] GPE0_STS */
+ NULL, /* [10] reserved */
+ NULL, /* [11] reserved */
+ NULL, /* [12] reserved */
+ southbridge_smi_tco, /* [13] TCO_STS */
+ southbridge_smi_periodic, /* [14] PERIODIC_STS */
+ NULL, /* [15] SERIRQ_SMI_STS */
+ NULL, /* [16] SMBUS_SMI_STS */
+ NULL, /* [17] LEGACY_USB2_STS */
+ NULL, /* [18] INTEL_USB2_STS */
+ NULL, /* [19] reserved */
+ NULL, /* [20] PCI_EXP_SMI_STS */
+ NULL, /* [21] reserved */
+ NULL, /* [22] reserved */
+ NULL, /* [23] reserved */
+ NULL, /* [24] reserved */
+ NULL, /* [25] reserved */
+ NULL, /* [26] SPI_STS */
+ NULL, /* [27] reserved */
+ NULL, /* [28] PUNIT */
+ NULL, /* [29] GUNIT */
+ NULL, /* [30] reserved */
+ NULL /* [31] reserved */
};
void southbridge_smi_handler(void)
@@ -433,7 +432,8 @@
int i;
uint32_t smi_sts;
- /* We need to clear the SMI status registers, or we won't see what's
+ /*
+ * We need to clear the SMI status registers, or we won't see what's
* happening in the following calls.
*/
smi_sts = clear_smi_status();
@@ -452,7 +452,9 @@
}
}
- /* The GPIO SMI events do not have a status bit in SMI_STS. Therefore,
- * these events need to be cleared and checked unconditionally. */
+ /*
+ * The GPIO SMI events do not have a status bit in SMI_STS. Therefore,
+ * these events need to be cleared and checked unconditionally.
+ */
mainboard_smi_gpi(clear_alt_status());
}
diff --git a/src/soc/intel/baytrail/smm.c b/src/soc/intel/baytrail/smm.c
index d16f918..be541da 100644
--- a/src/soc/intel/baytrail/smm.c
+++ b/src/soc/intel/baytrail/smm.c
@@ -76,13 +76,15 @@
printk(BIOS_DEBUG, "Enabling SMIs.\n");
if (!smm_save_params[SMM_SAVE_PARAM_PCIE_WAKE_ENABLE])
pm1_events |= PCIEXPWAK_DIS;
+
enable_pm1(pm1_events);
disable_gpe(PME_B0_EN);
/* Set up the GPIO route. */
smm_southcluster_route_gpios();
- /* Enable SMI generation:
+ /*
+ * Enable SMI generation:
* - on APMC writes (io 0xb2)
* - on writes to SLP_EN (sleep states)
* - on writes to GBL_RLS (bios commands)
diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c
index b7157c7..9a297aa 100644
--- a/src/soc/intel/baytrail/southcluster.c
+++ b/src/soc/intel/baytrail/southcluster.c
@@ -62,7 +62,7 @@
(base + size) < LPC_DEFAULT_IO_RANGE_UPPER)
return 1;
- /* This will return not in range for partial overlaps. */
+ /* This will return not in range for partial overlaps */
return 0;
}
@@ -294,13 +294,13 @@
if (mask != 0) {
write32(func_dis, read32(func_dis) | mask);
- /* Ensure posted write hits. */
+ /* Ensure posted write hits */
read32(func_dis);
}
if (mask2 != 0) {
write32(func_dis2, read32(func_dis2) | mask2);
- /* Ensure posted write hits. */
+ /* Ensure posted write hits */
read32(func_dis2);
}
}
@@ -314,9 +314,10 @@
pci_write_config8(dev, offset + 4, reg8);
}
-/* Parts of the audio subsystem are powered by the HDA device. Therefore, one
- * cannot put HDA into D3Hot. Instead perform this workaround to make some of
- * the audio paths work for LPE audio. */
+/*
+ * Parts of the audio subsystem are powered by the HDA device. Thus, one cannot put HDA into
+ * D3Hot. Instead, perform this workaround to make some of the audio paths work for LPE audio.
+ */
static void hda_work_around(struct device *dev)
{
u32 *gctl = (u32 *)(TEMP_BASE_ADDRESS + 0x8);
@@ -324,8 +325,10 @@
/* Need to set magic register 0x43 to 0xd7 in config space. */
pci_write_config8(dev, 0x43, 0xd7);
- /* Need to set bit 0 of GCTL to take the device out of reset. However,
- * that requires setting up the 64-bit BAR. */
+ /*
+ * Need to set bit 0 of GCTL to take the device out of reset.
+ * However, that requires setting up the 64-bit BAR.
+ */
pci_write_config32(dev, PCI_BASE_ADDRESS_0, TEMP_BASE_ADDRESS);
pci_write_config32(dev, PCI_BASE_ADDRESS_1, 0);
pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
@@ -338,8 +341,10 @@
{
unsigned int offset;
- /* Parts of the HDA block are used for LPE audio as well.
- * Therefore assume the HDA will never be put into D3Hot. */
+ /*
+ * Parts of the HDA block are used for LPE audio as well.
+ * Therefore assume the HDA will never be put into D3Hot.
+ */
if (dev->path.pci.devfn == PCI_DEVFN(HDA_DEV, HDA_FUNC)) {
hda_work_around(dev);
return 0;
@@ -352,8 +357,10 @@
return 0;
}
- /* For some reason some of the devices don't have the capability
- * pointer set correctly. Work around this by hard coding the offset. */
+ /*
+ * For some reason some of the devices don't have the capability pointer set correctly.
+ * Work around this by hard coding the offset.
+ */
switch (dev->path.pci.devfn) {
case PCI_DEVFN(SDIO_DEV, SDIO_FUNC):
offset = 0x80;
@@ -536,16 +543,16 @@
u8 *spi = (u8 *)SPI_BASE_ADDRESS;
struct spi_config cfg;
- /* Set the lock enable on the BIOS control register. */
+ /* Set the lock enable on the BIOS control register */
write32(bcr, read32(bcr) | BCR_LE);
- /* Set BIOS lock down bit controlling boot block size and swapping. */
+ /* Set BIOS lock down bit controlling boot block size and swapping */
write32(gcs, read32(gcs) | BILD);
- /* Lock sleep stretching policy and set SMI lock. */
+ /* Lock sleep stretching policy and set SMI lock */
write32(gen_pmcon2, read32(gen_pmcon2) | SLPSX_STR_POL_LOCK | SMI_LOCK);
- /* Set the CF9 lock. */
+ /* Set the CF9 lock */
write32(etr, read32(etr) | CF9LOCK);
if (mainboard_get_spi_config(&cfg) < 0) {
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