5 comments:
File src/mainboard/intel/coffeelake_rvp/chromeos_32MB.fmd:
Patch Set #3, Line 5: SI_GBE@0x81000 0x2000
Arthur, is this correct now?
It's not modified by this patch now.
File src/mainboard/intel/coffeelake_rvp/variants/cml_s/devicetree.cb:
Is this still applicable?
it's moved to overridetree, will ensure no newline at the end.
File src/mainboard/intel/coffeelake_rvp/variants/cml_s/overridetree.cb:
Patch Set #10, Line 73: register "PcieRpEnable[0]" = "0"
I think you can omit disabled PCIe root ports, as the default value is zero
will revise it
Patch Set #10, Line 91: register "PcieRpEnable[4]" = "1"
Maybe add a comment that these are for the Thunderbolt controller
will add a comment
Patch Set #10, Line 151: Tunderbolt
typo: missing "h" in Thunderbolt
Thanks. Good catch.
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