Michał Żygowski has uploaded this change for review.
soc/intel/braswell/smbus: Init SMBus
Using Intel southbridge common implementation to retrieve SPD from DIMMs
causes FSP memory init to hang. Initialize SMBus as in Intel SoC common
before issuing any transactions to let FSP properly initialize memory.
Also make Intel common southbridge smbus API compatible with SPD library.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I92a2c5a6d0b38e5658cfdc017041f12717dabdd5
---
M src/soc/intel/braswell/Makefile.inc
A src/soc/intel/braswell/include/soc/smbus.h
M src/soc/intel/braswell/romstage/romstage.c
A src/soc/intel/braswell/smbus.c
4 files changed, 92 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/32062/1
diff --git a/src/soc/intel/braswell/Makefile.inc b/src/soc/intel/braswell/Makefile.inc
index a538f7d..554af41 100644
--- a/src/soc/intel/braswell/Makefile.inc
+++ b/src/soc/intel/braswell/Makefile.inc
@@ -14,6 +14,7 @@
romstage-y += lpc_init.c
romstage-y += memmap.c
romstage-y += pmutil.c
+romstage-y += smbus.c
romstage-y += tsc_freq.c
postcar-y += tsc_freq.c
@@ -38,6 +39,7 @@
ramstage-y += sata.c
ramstage-y += scc.c
ramstage-y += sd.c
+ramstage-y += smbus.c
ramstage-y += smm.c
ramstage-y += southcluster.c
ramstage-y += spi.c
diff --git a/src/soc/intel/braswell/include/soc/smbus.h b/src/soc/intel/braswell/include/soc/smbus.h
new file mode 100644
index 0000000..f5075e1
--- /dev/null
+++ b/src/soc/intel/braswell/include/soc/smbus.h
@@ -0,0 +1,36 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 3mdeb
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+
+#ifndef _SOC_SMBUS_H_
+#define _SOC_SMBUS_H_
+
+#include <soc/pci_devs.h>
+
+#if !defined(__SIMPLE_DEVICE__)
+#include <device/device.h>
+#define PCH_DEV_SMBUS dev_find_slot(0, PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC))
+#else
+
+#include <device/pci_type.h>
+#define PCH_DEV_SMBUS PCI_DEV(0, SMBUS_DEV, SMBUS_FUNC)
+#endif
+
+#define HOSTC 0x40
+#define HST_EN (1 << 0)
+
+void smbus_common_init(void);
+
+#endif /* _SOC_SMBUS_H_ */
diff --git a/src/soc/intel/braswell/romstage/romstage.c b/src/soc/intel/braswell/romstage/romstage.c
index ca1eb40..6a0226e 100644
--- a/src/soc/intel/braswell/romstage/romstage.c
+++ b/src/soc/intel/braswell/romstage/romstage.c
@@ -40,6 +40,7 @@
#include <soc/lpc.h>
#include <soc/pci_devs.h>
#include <soc/romstage.h>
+#include <soc/smbus.h>
#include <soc/smm.h>
#include <soc/spi.h>
#include <build.h>
@@ -194,6 +195,7 @@
spi_init();
lpc_init();
+ smbus_common_init();
}
/* SOC initialization after RAM is enabled */
diff --git a/src/soc/intel/braswell/smbus.c b/src/soc/intel/braswell/smbus.c
new file mode 100644
index 0000000..454c3f6
--- /dev/null
+++ b/src/soc/intel/braswell/smbus.c
@@ -0,0 +1,52 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Intel Corporation.
+ * Copyright (C) 2019 3mdeb
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/early_smbus.h>
+#include <device/pci_def.h>
+#include <reg_script.h>
+#include <soc/iomap.h>
+#include <soc/smbus.h>
+#include <southbridge/intel/common/smbus.h>
+
+static const struct reg_script smbus_init_script[] = {
+ /* Set SMBus I/O base address */
+ REG_PCI_WRITE32(PCI_BASE_ADDRESS_4, SMBUS_BASE_ADDRESS),
+ /* Set SMBus enable */
+ REG_PCI_WRITE8(HOSTC, HST_EN),
+ /* Enable I/O access */
+ REG_PCI_WRITE16(PCI_COMMAND, PCI_COMMAND_IO),
+ /* Disable interrupts */
+ REG_IO_WRITE8(SMBUS_BASE_ADDRESS + SMBHSTCTL, 0),
+ /* Clear errors */
+ REG_IO_WRITE8(SMBUS_BASE_ADDRESS + SMBHSTSTAT, 0xff),
+ /* Indicate the end of this array by REG_SCRIPT_END */
+ REG_SCRIPT_END,
+};
+
+u8 smbus_read_byte(u32 smbus_dev, u8 addr, u8 offset)
+{
+ return do_smbus_read_byte(SMBUS_BASE_ADDRESS, addr, offset);
+}
+
+u8 smbus_write_byte(u32 smbus_dev, u8 addr, u8 offset, u8 value)
+{
+ return do_smbus_write_byte(SMBUS_BASE_ADDRESS, addr, offset, value);
+}
+
+void smbus_common_init(void)
+{
+ reg_script_run_on_dev(PCH_DEV_SMBUS, smbus_init_script);
+}
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