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1 comment:

• File src/soc/intel/common/pch/reset/reset.c:

  • Patch Set #2, Line 37: FSP_STATUS_RESET_REQUIRED_3

    I think this value is chipset FSP-dependent? I see that we use _3 for most but APL uses _5. Should there be a macro FSP_STATUS_GLOBAL_RESET which can be defined by SoCs as per their FSP implementation?

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