Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, V Sowmya, Vidya Gopalakrishnan, Vinay Kumar.
Hello Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik, V Sowmya, Vinay Kumar, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/85184?usp=email
to look at the new patch set (#5).
Change subject: mb/google/brya/var/trulo: Remove overriding of PL1 value to 20W ......................................................................
mb/google/brya/var/trulo: Remove overriding of PL1 value to 20W
The RAPL PL1 limit and MMIO PL1 max values should be set as per silicon TDP (6W for N150/N250, 15W for N355).
BUG=b:378623372 TEST=Build and boot on Trulo board. Verified PL1 value is updated in DTT and sysfs interfaces. Output with 15W silicon as below: cd /sys/class/powercap/ cat intel-rapl/intel-rapl:0/constraint_0_max_power_uw 15000000 cat intel-rapl/intel-rapl:0/constraint_0_power_limit_uw 15000000 cat intel-rapl-mmio/intel-rapl-mmio:0/constraint_0_max_power_uw 15000000 cat intel-rapl-mmio/intel-rapl-mmio:0/constraint_0_power_limit_uw 15000000
Change-Id: I798c4f10e10a579f470e00dbdb77a84619ad796a Signed-off-by: Vidya Gopalakrishnan vidya.gopalakrishnan@intel.com --- M src/mainboard/google/brya/variants/trulo/overridetree.cb 1 file changed, 4 insertions(+), 22 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/85184/5