Amanda Hwang has uploaded this change for review.

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hatch: Fix FPMCU pwr/rst gpio handling for mushu

Hatch moves power/reset pin control of FPMCU to var/board/ramstage.
So add this change in mushu.

BUG=b:147274277
TEST=emerge-hatch coreboot

Change-Id: I10c9b8f673618ddaddfeed86705f3c838e7021fd
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
---
M src/mainboard/google/hatch/variants/mushu/Makefile.inc
M src/mainboard/google/hatch/variants/mushu/gpio.c
A src/mainboard/google/hatch/variants/mushu/ramstage.c
3 files changed, 62 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/38340/1

diff --git a/src/mainboard/google/hatch/variants/mushu/Makefile.inc b/src/mainboard/google/hatch/variants/mushu/Makefile.inc
index a990b5a..0e7863d 100644
--- a/src/mainboard/google/hatch/variants/mushu/Makefile.inc
+++ b/src/mainboard/google/hatch/variants/mushu/Makefile.inc
@@ -21,3 +21,4 @@
 
 ramstage-y += gpio.c
 bootblock-y += gpio.c
+ramstage-y += ramstage.c
diff --git a/src/mainboard/google/hatch/variants/mushu/gpio.c b/src/mainboard/google/hatch/variants/mushu/gpio.c
index 09e1594..18cbc09 100644
--- a/src/mainboard/google/hatch/variants/mushu/gpio.c
+++ b/src/mainboard/google/hatch/variants/mushu/gpio.c
@@ -57,8 +57,6 @@
  * needed in this table.
  */
 static const struct pad_config early_gpio_table[] = {
-	/* A12 : FPMCU_RST_ODL */
-	PAD_CFG_GPO(GPP_A12, 0, DEEP),
 	/* B15 : H1_SLAVE_SPI_CS_L */
 	PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),
 	/* B16 : H1_SLAVE_SPI_CLK */
@@ -88,3 +86,32 @@
 	*num = ARRAY_SIZE(early_gpio_table);
 	return early_gpio_table;
 }
+
+/*
+ * Default GPIO settings before entering non-S5 sleep states.
+ * Configure A12: FPMCU_RST_ODL as GPO before entering sleep.
+ * This guarantees that A12's native3 function is disabled.
+ * See commit c41b0e8ea3b2714bf6d6d88a6b66c333c6919f07.
+ */
+static const struct pad_config default_sleep_gpio_table[] = {
+	PAD_CFG_GPO(GPP_A12, 1, DEEP), /* FPMCU_RST_ODL */
+};
+
+/*
+ * GPIO settings before entering S5, which are same as default_sleep_gpio_table
+ * but also, turn off FPMCU.
+ */
+static const struct pad_config s5_sleep_gpio_table[] = {
+	PAD_CFG_GPO(GPP_A12, 0, DEEP), /* FPMCU_RST_ODL */
+	PAD_CFG_GPO(GPP_C11, 0, DEEP), /* PCH_FP_PWR_EN */
+};
+
+const struct pad_config *variant_sleep_gpio_table(u8 slp_typ, size_t *num)
+{
+	if (slp_typ == ACPI_S5) {
+		*num = ARRAY_SIZE(s5_sleep_gpio_table);
+		return s5_sleep_gpio_table;
+	}
+	*num = ARRAY_SIZE(default_sleep_gpio_table);
+	return default_sleep_gpio_table;
+}
diff --git a/src/mainboard/google/hatch/variants/mushu/ramstage.c b/src/mainboard/google/hatch/variants/mushu/ramstage.c
new file mode 100644
index 0000000..9b919fc
--- /dev/null
+++ b/src/mainboard/google/hatch/variants/mushu/ramstage.c
@@ -0,0 +1,32 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2019 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <delay.h>
+#include <gpio.h>
+#include <baseboard/variants.h>
+#include <soc/gpio.h>
+
+void variant_ramstage_init(void)
+{
+	/*
+	 * Enable power to FPMCU, wait for power rail to stabilize,
+	 * and then deassert FPMCU reset.
+	 * Waiting for the power rail to stabilize can take a while,
+	 * a minimum of 400us on Kohaku.
+	 */
+	gpio_output(GPP_C11, 1);
+	mdelay(1);
+	gpio_output(GPP_A12, 1);
+}

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