Bernardo Perez Priego uploaded patch set #18 to this change.

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soc/intel/common: Add romstage common stage file

This patch will ensures all intel soc is using common stage
files to make coreboot design flow align across all socs.

CPU, SA, PCH, MCH programming sequence might be different between
socs but the function call should route from same location across
all soc.

Signed-off-by: Bernardo Perez Priego <>
Change-Id: I06d43ac29f5e87ce731a470e5e145adea07ece4c
M src/soc/intel/common/Kconfig.common
A src/soc/intel/common/basecode/include/intelbasecode/romstage.h
A src/soc/intel/common/basecode/romstage/Kconfig
A src/soc/intel/common/basecode/romstage/
A src/soc/intel/common/basecode/romstage/romstage.c
5 files changed, 297 insertions(+), 0 deletions(-)

git pull ssh:// refs/changes/28/37628/18

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I06d43ac29f5e87ce731a470e5e145adea07ece4c
Gerrit-Change-Number: 37628
Gerrit-PatchSet: 18
Gerrit-Owner: Bernardo Perez Priego <>
Gerrit-Reviewer: Aamir Bohra <>
Gerrit-Reviewer: Bernardo Perez Priego <>
Gerrit-Reviewer: Bora Guvendik <>
Gerrit-Reviewer: Martin Roth <>
Gerrit-Reviewer: Patrick Georgi <>
Gerrit-Reviewer: Patrick Rudolph <>
Gerrit-Reviewer: Selma Bensaid <>
Gerrit-Reviewer: Subrata Banik <>
Gerrit-Reviewer: Usha P <>
Gerrit-Reviewer: Varun Joshi <>
Gerrit-Reviewer: build bot (Jenkins) <>
Gerrit-CC: Paul Menzel <>
Gerrit-MessageType: newpatchset