Arthur Heymans has uploaded this change for review.

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sb/intel/common: Add code to configure who decodes IO 0x80

Change-Id: Ieb973c369c0061867320c255df5ae85fb5101276
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
---
M src/southbridge/intel/common/Kconfig
M src/southbridge/intel/common/Makefile.inc
A src/southbridge/intel/common/post.c
A src/southbridge/intel/common/post.h
4 files changed, 34 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/47164/1

diff --git a/src/southbridge/intel/common/Kconfig b/src/southbridge/intel/common/Kconfig
index 3030d25..74f0252 100644
--- a/src/southbridge/intel/common/Kconfig
+++ b/src/southbridge/intel/common/Kconfig
@@ -105,3 +105,6 @@
 	hex
 	depends on SOUTHBRIDGE_INTEL_COMMON_SMBUS
 	default 0x400
+
+config SOUTHBRIDGE_INTEL_COMMON_POST
+	def_bool n
diff --git a/src/southbridge/intel/common/Makefile.inc b/src/southbridge/intel/common/Makefile.inc
index 1ededd2..50dda9b 100644
--- a/src/southbridge/intel/common/Makefile.inc
+++ b/src/southbridge/intel/common/Makefile.inc
@@ -3,6 +3,8 @@
 # CONFIG_HAVE_INTEL_FIRMWARE protects doing anything to the build.
 subdirs-y += firmware
 
+bootblock-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_POST) += post.c
+
 all-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET) += reset.c
 
 romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS) += early_smbus.c
diff --git a/src/southbridge/intel/common/post.c b/src/southbridge/intel/common/post.c
new file mode 100644
index 0000000..96155d1
--- /dev/null
+++ b/src/southbridge/intel/common/post.c
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <assert.h>
+
+#include "rcba.h"
+
+#define GCS 0x3410
+#define RPR (1 << 2)
+
+void configure_port80(void)
+{
+	if (CONFIG(POST_DEVICE_LPC))
+		RCBA32_AND_OR(GCS, ~RPR, 0);
+	else if (CONFIG(POST_DEVICE_PCI_PCIE))
+		RCBA32_AND_OR(GCS, RPR, RPR);
+}
diff --git a/src/southbridge/intel/common/post.h b/src/southbridge/intel/common/post.h
new file mode 100644
index 0000000..f64fce5
--- /dev/null
+++ b/src/southbridge/intel/common/post.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef SOUTHBRIDGE_INTEL_COMMON_POST_H
+#define SOUTHBRIDGE_INTEL_COMMON_POST_H
+
+/* Configure where IO port 0x80 writes (POST) get forwarded (PCI/LPC).
+ * Note that port 0x90 writes which aliases port 0x80 always get forwarded
+ * to LPC.
+ */
+void configure_port80(void);
+
+#endif
+

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