Arthur Heymans has uploaded this change for review.

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[WIP]soc/intel/xeon_sp/cpx: Run romstage from CAR

Tested works on ocp/deltalake

Change-Id: Ie51677dd1f2be7200098bb83f756ddb0dbe69e44
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
---
M src/soc/intel/xeon_sp/Kconfig
M src/soc/intel/xeon_sp/cpx/Kconfig
2 files changed, 10 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/48736/1
diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig
index 664f960..907e1f9 100644
--- a/src/soc/intel/xeon_sp/Kconfig
+++ b/src/soc/intel/xeon_sp/Kconfig
@@ -65,6 +65,7 @@
select HAVE_SMI_HANDLER
select X86_SMM_LOADER_VERSION2
select REG_SCRIPT
+ select NO_XIP_EARLY_STAGES

config MAINBOARD_USES_FSP2_0
bool
diff --git a/src/soc/intel/xeon_sp/cpx/Kconfig b/src/soc/intel/xeon_sp/cpx/Kconfig
index 43337b5..a31d372 100644
--- a/src/soc/intel/xeon_sp/cpx/Kconfig
+++ b/src/soc/intel/xeon_sp/cpx/Kconfig
@@ -31,11 +31,11 @@

config DCACHE_RAM_BASE
hex
- default 0xfe800000
+ default 0xfe940000

config DCACHE_RAM_SIZE
hex
- default 0x1fff00
+ default 0xbff00
help
The size of the cache-as-ram region required during bootblock
and/or romstage. FSP-T reserves the upper 0x100 for
@@ -43,7 +43,7 @@

config DCACHE_BSP_STACK_SIZE
hex
- default 0x140000
+ default 0x40000
help
The amount of anticipated stack usage in CAR by bootblock and
other stages. It needs to include FSP-M stack requirement and
@@ -51,6 +51,12 @@
says this needs to be 256KiB, but practice show this needs to
be a lot more.

+config ROMSTAGE_ADDR
+ hex
+ default 0xfe9d0000
+ help
+ The base address (in CAR) where romstage should be linked.
+
config CPU_MICROCODE_CBFS_LOC
hex
default 0xfff0fdc0

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ie51677dd1f2be7200098bb83f756ddb0dbe69e44
Gerrit-Change-Number: 48736
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur@aheymans.xyz>
Gerrit-MessageType: newchange