Hannah Williams has uploaded this change for review. ( https://review.coreboot.org/20755
Change subject: soc/intel/apollolake: Add CNVI and PCIE IRQs for GLK ......................................................................
soc/intel/apollolake: Add CNVI and PCIE IRQs for GLK
Change-Id: I0387ccf6970e6169cbebd232ae210731338d0900 Signed-off-by: Hannah Williams hannah.williams@intel.com --- M src/soc/intel/apollolake/acpi/pci_irqs.asl M src/soc/intel/apollolake/acpi/soc_int.asl 2 files changed, 13 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/20755/1
diff --git a/src/soc/intel/apollolake/acpi/pci_irqs.asl b/src/soc/intel/apollolake/acpi/pci_irqs.asl index 22878c6..2475db3 100644 --- a/src/soc/intel/apollolake/acpi/pci_irqs.asl +++ b/src/soc/intel/apollolake/acpi/pci_irqs.asl @@ -30,6 +30,15 @@ Package(){0x000FFFFF, 0, 0, CSE_INT}, Package(){0x0011FFFF, 0, 0, ISH_INT}, Package(){0x0012FFFF, 0, 0, SATA_INT}, +#if IS_ENABLED(CONFIG_SOC_INTEL_GLK) + Package(){0x000CFFFF, 0, 0, CNVI_INT}, + Package(){0x0013FFFF, 0, 0, PIRQF_INT}, + Package(){0x0013FFFF, 1, 0, PIRQF_INT}, + Package(){0x0013FFFF, 2, 0, PIRQF_INT}, + Package(){0x0013FFFF, 3, 0, PIRQF_INT}, + Package(){0x0014FFFF, 0, 0, PIRQG_INT}, + Package(){0x0014FFFF, 1, 0, PIRQG_INT}, +#else Package(){0x0013FFFF, 0, 0, PIRQA_INT}, Package(){0x0013FFFF, 1, 0, PIRQB_INT}, Package(){0x0013FFFF, 2, 0, PIRQC_INT}, @@ -38,6 +47,7 @@ Package(){0x0014FFFF, 1, 0, PIRQC_INT}, Package(){0x0014FFFF, 2, 0, PIRQD_INT}, Package(){0x0014FFFF, 3, 0, PIRQA_INT}, +#endif Package(){0x0015FFFF, 0, 0, XHCI_INT}, Package(){0x0015FFFF, 1, 0, XDCI_INT}, Package(){0x0016FFFF, 0, 0, I2C0_INT}, diff --git a/src/soc/intel/apollolake/acpi/soc_int.asl b/src/soc/intel/apollolake/acpi/soc_int.asl index c643244..11b5460 100644 --- a/src/soc/intel/apollolake/acpi/soc_int.asl +++ b/src/soc/intel/apollolake/acpi/soc_int.asl @@ -36,6 +36,8 @@ #define SMBUS_INT 20 /* PIRQE */ #define CSE_INT 20 /* PIRQE */ #define IUNIT_INT 21 /* PIRQF */ +#define PIRQF_INT 21 +#define PIRQG_INT 22 #define PUNIT_INT 24 #define AUDIO_INT 25 #define ISH_INT 26 @@ -54,5 +56,6 @@ #define EMMC_INT 39 #define PMC_INT 40 #define SDIO_INT 42 +#define CNVI_INT 44
#endif /* _SOC_INT_DEFINE_ASL_ */