John Su has uploaded this change for review.

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mb/google/zork/variants/vilboz: Diasable ASPM L1.2 for SD card reader

From bayhub vendor feedback, OZ711LV2 only set to L1.1 for AMD project,
because the reason is AMD’s L1.2 capability is not good causing device lost
in past experience,so vilboz need set L1.1 in RC and device both side.

BUG=b:177955523
BRANCH=zork
TEST=check PCIE_L1_PM_SUB_CNTL 0x378[3:0]=0xA

Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: I2f24c08411eabb1579c76aaafbe3eb054db54f69
---
M src/mainboard/google/zork/variants/vilboz/variant.c
1 file changed, 42 insertions(+), 42 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/50280/1

diff --git a/src/mainboard/google/zork/variants/vilboz/variant.c b/src/mainboard/google/zork/variants/vilboz/variant.c
index eb49c47..8a3ed7c 100644
--- a/src/mainboard/google/zork/variants/vilboz/variant.c
+++ b/src/mainboard/google/zork/variants/vilboz/variant.c
@@ -24,48 +24,48 @@
 };
 
 static const fsp_dxio_descriptor vilboz_dxio_descriptors[] = {
-        {
-                // NVME SSD
-                .port_present = true,
-                .engine_type = PCIE_ENGINE,
-                .start_logical_lane = 4,
-                .end_logical_lane = 5,
-                .device_number = 1,
-                .function_number = 7,
-                .link_aspm = ASPM_L1,
-                .link_aspm_L1_1 = true,
-                .link_aspm_L1_2 = true,
-                .turn_off_unused_lanes = true,
-                .clk_req = CLK_REQ2,
-        },
-        {
-                // WLAN
-                .port_present = true,
-                .engine_type = PCIE_ENGINE,
-                .start_logical_lane = 0,
-                .end_logical_lane = 0,
-                .device_number = 1,
-                .function_number = 2,
-                .link_aspm = ASPM_L1,
-                .link_aspm_L1_1 = true,
-                .link_aspm_L1_2 = true,
-                .turn_off_unused_lanes = true,
-                .clk_req = CLK_REQ0,
-        },
-        {
-                // SD Reader
-                .port_present = true,
-                .engine_type = PCIE_ENGINE,
-                .start_logical_lane = 1,
-                .end_logical_lane = 1,
-                .device_number = 1,
-                .function_number = 3,
-                .link_aspm = ASPM_L1,
-                .link_aspm_L1_1 = true,
-                .link_aspm_L1_2 = false,
-                .turn_off_unused_lanes = true,
-                .clk_req = CLK_REQ1,
-        }
+	{
+		// NVME SSD
+		.port_present = true,
+		.engine_type = PCIE_ENGINE,
+		.start_logical_lane = 4,
+		.end_logical_lane = 5,
+		.device_number = 1,
+		.function_number = 7,
+		.link_aspm = ASPM_L1,
+		.link_aspm_L1_1 = true,
+		.link_aspm_L1_2 = true,
+		.turn_off_unused_lanes = true,
+		.clk_req = CLK_REQ2,
+	},
+	{
+		// WLAN
+		.port_present = true,
+		.engine_type = PCIE_ENGINE,
+		.start_logical_lane = 0,
+		.end_logical_lane = 0,
+		.device_number = 1,
+		.function_number = 2,
+		.link_aspm = ASPM_L1,
+		.link_aspm_L1_1 = true,
+		.link_aspm_L1_2 = true,
+		.turn_off_unused_lanes = true,
+		.clk_req = CLK_REQ0,
+	},
+	{
+		// SD Reader
+		.port_present = true,
+		.engine_type = PCIE_ENGINE,
+		.start_logical_lane = 1,
+		.end_logical_lane = 1,
+		.device_number = 1,
+		.function_number = 3,
+		.link_aspm = ASPM_L1,
+		.link_aspm_L1_1 = true,
+		.link_aspm_L1_2 = false,
+		.turn_off_unused_lanes = true,
+		.clk_req = CLK_REQ1,
+	}
 };
 
 void variant_get_dxio_ddi_descriptors(const fsp_dxio_descriptor **dxio_descs,

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