EricR Lai has uploaded this change for review.

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soc/intel/alderlake: Revise PCIE port config

PCIE ClkSrcUsage and ClkSrcClkReq are always confusing in devicetree.
Make it easier to just fill the number from schematics.

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I0b390e43f8e99b19cfad178139b86a2f77d7a57b
---
M src/soc/intel/alderlake/chip.h
M src/soc/intel/alderlake/romstage/fsp_params.c
2 files changed, 12 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/48340/1

diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h
index 428fd4d..38d1c3c 100644
--- a/src/soc/intel/alderlake/chip.h
+++ b/src/soc/intel/alderlake/chip.h
@@ -119,7 +119,12 @@
 	uint8_t PchHdaIDispCodecDisconnect;
 
 	/* PCIe Root Ports */
-	uint8_t PcieRpEnable[CONFIG_MAX_ROOT_PORTS];
+	struct {
+		uint8_t enabled,
+		uint8_t clksrc,
+		uint8_t clkreq,
+	} PcieRp[CONFIG_MAX_ROOT_PORTS];
+
 	uint8_t PcieRpHotPlug[CONFIG_MAX_ROOT_PORTS];
 	/* PCIe output clocks type to PCIe devices.
 	 * 0-23: PCH rootport, 0x70: LAN, 0x80: unspecified but in use,
diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c
index 7e842a2..7b36e90 100644
--- a/src/soc/intel/alderlake/romstage/fsp_params.c
+++ b/src/soc/intel/alderlake/romstage/fsp_params.c
@@ -41,9 +41,13 @@
 		/* Set CpuRatio to match existing MSR value */
 		m_cfg->CpuRatio = (rdmsr(MSR_FLEX_RATIO).lo >> 8) & 0xff;
 
-	for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) {
-		if (config->PcieRpEnable[i])
+	for (i = 0; i < CONFIG_MAX_ROOT_PORTS; i++) {
+		if (config->PcieRp[i].enabled)
+		{
 			mask |= (1 << i);
+			config->PcieClkSrcClkReq[PcieRp[i].clkreq] = PcieRp[i].clksrc;
+			config->PcieClkSrcUsage[PcieRp[i].clksrc] = i;
+		}
 	}
 	m_cfg->PcieRpEnableMask = mask;
 

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