Shaunak Saha has uploaded this change for review.

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mb/google/volteer: Implement variant_devtree_update for volteer sku's

HybridStorageMode FSP UPD needs to be set only for optane storage.
Enabling HybridStorageMode causes some extra delay in FspSiliconInit due
to HECI command and hence is avoided for NVMe and SATA scenerios. This change
disables "HybridStorageMode" by default from baseboard devicetree. Any
volteer variant which is using optane should enable "HybridStorageMode" from
the override devicetree file.This change also provides an implementation of
variant_devtree_update() for volteer that enables HybridStorageMode for
SKU ID = 3 and 5.

BUG=b:158573805
TEST=Verify HybridStorageMode is disabled when SKU ID != 3 or 5 and
enabled for those 2 sku's only.

Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Change-Id: I5c3bcfafe1710155bb47f706c3568dd9500c1975
---
M src/mainboard/google/volteer/Makefile.inc
A src/mainboard/google/volteer/ramstage.c
M src/mainboard/google/volteer/variants/baseboard/devicetree.cb
M src/mainboard/google/volteer/variants/baseboard/include/baseboard/variants.h
M src/mainboard/google/volteer/variants/volteer/Makefile.inc
A src/mainboard/google/volteer/variants/volteer/variant.c
6 files changed, 39 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/44261/1
diff --git a/src/mainboard/google/volteer/Makefile.inc b/src/mainboard/google/volteer/Makefile.inc
index c01f993..b5579a7 100644
--- a/src/mainboard/google/volteer/Makefile.inc
+++ b/src/mainboard/google/volteer/Makefile.inc
@@ -10,6 +10,7 @@
ramstage-y += ec.c
ramstage-$(CONFIG_FW_CONFIG) += fw_config.c
ramstage-y += mainboard.c
+ramstage-y += ramstage.c

smm-y += smihandler.c

diff --git a/src/mainboard/google/volteer/ramstage.c b/src/mainboard/google/volteer/ramstage.c
new file mode 100644
index 0000000..084e69e
--- /dev/null
+++ b/src/mainboard/google/volteer/ramstage.c
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <baseboard/variants.h>
+#include <soc/ramstage.h>
+
+void mainboard_silicon_init_params(FSP_S_CONFIG *params)
+{
+ variant_devtree_update();
+}
+
+void __weak variant_devtree_update(void)
+{
+ /* Override dev tree settings per board */
+}
+
diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
index 53bbe5a..ccd1877 100644
--- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
@@ -81,7 +81,9 @@
# Enable Optane PCIE 11 using clk 0
register "PcieRpEnable[10]" = "1"
register "PcieRpLtrEnable[10]" = "1"
- register "HybridStorageMode" = "1"
+ # Disable it by default. Device tree overwrite needs to enable this feature
+ # for platforms using Optane memory.
+ register "HybridStorageMode" = "0"

# Enable SD Card PCIE 8 using clk 3
register "PcieRpEnable[7]" = "1"
diff --git a/src/mainboard/google/volteer/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/variants.h
index 2f90a42..aa8ea27 100644
--- a/src/mainboard/google/volteer/variants/baseboard/include/baseboard/variants.h
+++ b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/variants.h
@@ -21,4 +21,6 @@
const struct lpddr4x_cfg *variant_memory_params(void);
int variant_memory_sku(void);

+void variant_devtree_update(void);
+
#endif /* __BASEBOARD_VARIANTS_H__ */
diff --git a/src/mainboard/google/volteer/variants/volteer/Makefile.inc b/src/mainboard/google/volteer/variants/volteer/Makefile.inc
index 13269db..04af3ae 100644
--- a/src/mainboard/google/volteer/variants/volteer/Makefile.inc
+++ b/src/mainboard/google/volteer/variants/volteer/Makefile.inc
@@ -3,3 +3,4 @@
bootblock-y += gpio.c

ramstage-y += gpio.c
+ramstage-y += variant.c
diff --git a/src/mainboard/google/volteer/variants/volteer/variant.c b/src/mainboard/google/volteer/variants/volteer/variant.c
new file mode 100644
index 0000000..8d3adef
--- /dev/null
+++ b/src/mainboard/google/volteer/variants/volteer/variant.c
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <baseboard/variants.h>
+#include <chip.h>
+#include <ec/google/chromeec/ec.h>
+
+void variant_devtree_update(void)
+{
+ uint32_t sku_id;
+ config_t *cfg = config_of_soc();
+
+ if (google_chromeec_cbi_get_sku_id(&sku_id))
+ return;
+
+ if ((sku_id == 3) || (sku_id == 5))
+ cfg->HybridStorageMode = 1;
+}

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I5c3bcfafe1710155bb47f706c3568dd9500c1975
Gerrit-Change-Number: 44261
Gerrit-PatchSet: 1
Gerrit-Owner: Shaunak Saha <shaunak.saha@intel.com>
Gerrit-MessageType: newchange