Matt DeVillier has uploaded this change for review.

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drivers/fsp 1.1: clean up Kconfig options

Now that support has been added for using the public FSP
repo for Braswell platform, clean up Kconfig options and
set sane defaults when using it.

The following changes have been made:
 - add option to use the 3rdparty/fsp repo for Braswell platform
 - reorder FSP 1.1 Kconfig entries for improved flow/readability
 - set the default path for the FSP binary based on use of FSP
   repo and platform
 - set the CBFS location for the FSP binary based on platform

Change-Id: Ie2f732bf0ac4d4551908caa56360b8bb2869b4c7
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
---
M src/drivers/intel/fsp1_1/Kconfig
1 file changed, 27 insertions(+), 14 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/32535/1

diff --git a/src/drivers/intel/fsp1_1/Kconfig b/src/drivers/intel/fsp1_1/Kconfig
index 2575577..02ae4de 100644
--- a/src/drivers/intel/fsp1_1/Kconfig
+++ b/src/drivers/intel/fsp1_1/Kconfig
@@ -25,8 +25,15 @@
 
 comment "Intel FSP 1.1"
 
+config FSP_USE_REPO
+	bool "Use FSP binary from 3rdparty/fsp repo"
+	select HAVE_FSP_BIN
+	depends on SOC_INTEL_BRASWELL
+	default n if USE_GOOGLE_FSP
+	default y
+
 config HAVE_FSP_BIN
-	bool "Should the Intel FSP binary be added to the flash image"
+	bool "Add Intel FSP binary to flash image"
 	help
 	  Select this option to add an Intel FSP binary to
 	  the resulting coreboot image.
@@ -34,6 +41,25 @@
 	  Note: Without this binary, coreboot builds relying on the FSP
 	  will not boot
 
+config FSP_FILE
+	string
+	prompt "Intel FSP binary path and filename" if !FSP_USE_REPO
+	depends on HAVE_FSP_BIN
+	default "3rdparty/fsp/BraswellFspBinPkg/FspBin/BSWFSP.fd" if FSP_USE_REPO && SOC_INTEL_BRASWELL
+	default ""
+	help
+	  The path and filename of the Intel FSP binary for this platform.
+
+config FSP_LOC
+	hex "Intel FSP Binary location in CBFS"
+	default 0xff6e0000 if SOC_INTEL_BRASWELL && USE_GOOGLE_FSP
+	default 0xfff20000 if SOC_INTEL_BRASWELL
+	default 0xffee0000 if SOC_INTEL_SKYLAKE
+	help
+	  The location in CBFS that the FSP is located. This must match the
+	  value that is set in the FSP binary.  If the FSP needs to be moved,
+	  rebase the FSP with Intel's BCT (tool).
+
 config CPU_MICROCODE_CBFS_LEN
 	hex "Microcode update region length in bytes"
 	default 0x0
@@ -47,19 +73,6 @@
 	  The location (base address) in CBFS that contains the microcode update
 	  binary.
 
-config FSP_FILE
-	string "Intel FSP binary path and filename"
-	help
-	  The path and filename of the Intel FSP binary for this platform.
-
-config FSP_LOC
-	hex "Intel FSP Binary location in CBFS"
-	default 0xffee0000
-	help
-	  The location in CBFS that the FSP is located. This must match the
-	  value that is set in the FSP binary.  If the FSP needs to be moved,
-	  rebase the FSP with Intel's BCT (tool).
-
 config DISPLAY_HOBS
 	bool "Display hand-off-blocks (HOBs)"
 	default n

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