Arthur Heymans has uploaded this change for review.
soc/intel/common: Rename save state accessors
This avoids name collision with follow-up code that intends to
reuse these names and replace this code.
Change-Id: Ib24ab09e7f35bb231a8069905860c612d5e35454
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
---
M src/soc/intel/apollolake/smihandler.c
M src/soc/intel/cannonlake/smihandler.c
M src/soc/intel/common/block/include/intelblocks/smihandler.h
M src/soc/intel/common/block/smm/smihandler.c
M src/soc/intel/common/block/smm/smitraphandler.c
M src/soc/intel/icelake/smihandler.c
M src/soc/intel/skylake/smihandler.c
M src/soc/intel/tigerlake/smihandler.c
8 files changed, 71 insertions(+), 71 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/37110/1
diff --git a/src/soc/intel/apollolake/smihandler.c b/src/soc/intel/apollolake/smihandler.c
index 53d2b7e..f26d8ba 100644
--- a/src/soc/intel/apollolake/smihandler.c
+++ b/src/soc/intel/apollolake/smihandler.c
@@ -29,7 +29,7 @@
return 1;
}
-const struct smm_save_state_ops *get_smm_save_state_ops(void)
+const struct intel_smm_save_state_ops *get_smm_save_state_ops(void)
{
return &em64t100_smm_ops;
}
diff --git a/src/soc/intel/cannonlake/smihandler.c b/src/soc/intel/cannonlake/smihandler.c
index 4d0b241..1d57c7e 100644
--- a/src/soc/intel/cannonlake/smihandler.c
+++ b/src/soc/intel/cannonlake/smihandler.c
@@ -32,7 +32,7 @@
#define CSME0_BAR 0x0
#define CSME0_FID 0xb0
-const struct smm_save_state_ops *get_smm_save_state_ops(void)
+const struct intel_smm_save_state_ops *get_smm_save_state_ops(void)
{
return &em64t101_smm_ops;
}
diff --git a/src/soc/intel/common/block/include/intelblocks/smihandler.h b/src/soc/intel/common/block/include/intelblocks/smihandler.h
index d8520f1..afe8505 100644
--- a/src/soc/intel/common/block/include/intelblocks/smihandler.h
+++ b/src/soc/intel/common/block/include/intelblocks/smihandler.h
@@ -25,32 +25,32 @@
/*
* The register value is used with get_reg and set_reg
*/
-enum smm_reg {
- RAX,
- RBX,
- RCX,
- RDX,
+enum intel_smm_reg {
+ SMM_RAX,
+ SMM_RBX,
+ SMM_RCX,
+ SMM_RDX,
};
-struct smm_save_state_ops {
+struct intel_smm_save_state_ops {
/* return io_misc_info from SMM Save State Area */
uint32_t (*get_io_misc_info)(void *state);
/* return value of the requested register from
* SMM Save State Area
*/
- uint64_t (*get_reg)(void *state, enum smm_reg reg);
+ uint64_t (*get_reg)(void *state, enum intel_smm_reg reg);
- void (*set_reg)(void *state, enum smm_reg reg, uint64_t val);
+ void (*set_reg)(void *state, enum intel_smm_reg reg, uint64_t val);
};
-typedef void (*smi_handler_t)(const struct smm_save_state_ops *save_state_ops);
+typedef void (*smi_handler_t)(const struct intel_smm_save_state_ops *save_state_ops);
/*
* SOC SMI Handler has to provide this structure which has methods to access
* the SOC specific SMM Save State Area
*/
-const struct smm_save_state_ops *get_smm_save_state_ops(void);
+const struct intel_smm_save_state_ops *get_smm_save_state_ops(void);
/*
* southbridge_smi should be defined inside SOC specific code and should have
@@ -67,7 +67,7 @@
* soc/intel/common/block/smm/smihandler.c
*/
void smihandler_southbridge_sleep(
- const struct smm_save_state_ops *save_state_ops);
+ const struct intel_smm_save_state_ops *save_state_ops);
/*
* This function should be implemented in SOC specific code to handle
@@ -75,7 +75,7 @@
* soc/intel/common/block/smm/smihandler.c
*/
void smihandler_southbridge_apmc(
- const struct smm_save_state_ops *save_state_ops);
+ const struct intel_smm_save_state_ops *save_state_ops);
/*
* This function should be implemented in SOC specific code to handle
@@ -83,7 +83,7 @@
* soc/intel/common/block/smm/smihandler.c
*/
void smihandler_southbridge_pm1(
- const struct smm_save_state_ops *save_state_ops);
+ const struct intel_smm_save_state_ops *save_state_ops);
/*
* This function should be implemented in SOC specific code to handle
@@ -91,7 +91,7 @@
* soc/intel/common/block/smm/smihandler.c
*/
void smihandler_southbridge_gpe0(
- const struct smm_save_state_ops *save_state_ops);
+ const struct intel_smm_save_state_ops *save_state_ops);
/*
* This function should be implemented in SOC specific code to handle
@@ -99,7 +99,7 @@
* soc/intel/common/block/smm/smihandler.c
*/
void smihandler_southbridge_mc(
- const struct smm_save_state_ops *save_state_ops);
+ const struct intel_smm_save_state_ops *save_state_ops);
/*
* This function should be implemented in SOC specific code to handle
@@ -107,14 +107,14 @@
* soc/intel/common/block/smm/smihandler.c
*/
void smihandler_southbridge_monitor(
- const struct smm_save_state_ops *save_state_ops);
+ const struct intel_smm_save_state_ops *save_state_ops);
/*
* This function should be implemented in SOC specific code to handle
* SMI_TCO event. The default functionality is provided in
* soc/intel/common/block/smm/smihandler.c
*/
void smihandler_southbridge_tco(
- const struct smm_save_state_ops *save_state_ops);
+ const struct intel_smm_save_state_ops *save_state_ops);
/*
* This function should be implemented in SOC specific code to handle
@@ -122,7 +122,7 @@
* soc/intel/common/block/smm/smihandler.c
*/
void smihandler_southbridge_periodic(
- const struct smm_save_state_ops *save_state_ops);
+ const struct intel_smm_save_state_ops *save_state_ops);
/*
* This function should be implemented in SOC specific code to handle
@@ -130,7 +130,7 @@
* soc/intel/common/block/smm/smihandler.c
*/
void smihandler_southbridge_gpi(
- const struct smm_save_state_ops *save_state_ops);
+ const struct intel_smm_save_state_ops *save_state_ops);
/*
* This function should be implemented in SOC specific code to handle
@@ -138,7 +138,7 @@
* soc/intel/common/block/smm/smihandler.c
*/
void smihandler_southbridge_espi(
- const struct smm_save_state_ops *save_state_ops);
+ const struct intel_smm_save_state_ops *save_state_ops);
/*
* Returns gnvs pointer within SMM context
@@ -173,7 +173,7 @@
/* Mainboard handler for ESPI EMIs */
void mainboard_smi_espi_handler(void);
-extern const struct smm_save_state_ops em64t100_smm_ops;
+extern const struct intel_smm_save_state_ops em64t100_smm_ops;
-extern const struct smm_save_state_ops em64t101_smm_ops;
+extern const struct intel_smm_save_state_ops em64t101_smm_ops;
#endif
diff --git a/src/soc/intel/common/block/smm/smihandler.c b/src/soc/intel/common/block/smm/smihandler.c
index 0581d23..d76fb0a 100644
--- a/src/soc/intel/common/block/smm/smihandler.c
+++ b/src/soc/intel/common/block/smm/smihandler.c
@@ -87,7 +87,7 @@
/* Common Functions */
-static void *find_save_state(const struct smm_save_state_ops *save_state_ops,
+static void *find_save_state(const struct intel_smm_save_state_ops *save_state_ops,
int cmd)
{
int node;
@@ -111,7 +111,7 @@
if (((io_misc_info >> 16) & 0xff) != APM_CNT)
continue;
/* Check AL against the requested command */
- reg_al = save_state_ops->get_reg(state, RAX);
+ reg_al = save_state_ops->get_reg(state, SMM_RAX);
if (reg_al != cmd)
continue;
break;
@@ -179,7 +179,7 @@
void smihandler_southbridge_sleep(
- const struct smm_save_state_ops *save_state_ops)
+ const struct intel_smm_save_state_ops *save_state_ops)
{
uint32_t reg32;
uint8_t slp_typ;
@@ -275,7 +275,7 @@
}
static void southbridge_smi_gsmi(
- const struct smm_save_state_ops *save_state_ops)
+ const struct intel_smm_save_state_ops *save_state_ops)
{
u8 sub_command, ret;
void *io_smi = NULL;
@@ -285,19 +285,19 @@
if (!io_smi)
return;
/* Command and return value in EAX */
- sub_command = (save_state_ops->get_reg(io_smi, RAX) >> 8)
+ sub_command = (save_state_ops->get_reg(io_smi, SMM_RAX) >> 8)
& 0xff;
/* Parameter buffer in EBX */
- reg_ebx = save_state_ops->get_reg(io_smi, RBX);
+ reg_ebx = save_state_ops->get_reg(io_smi, SMM_RBX);
/* drivers/elog/gsmi.c */
ret = gsmi_exec(sub_command, ®_ebx);
- save_state_ops->set_reg(io_smi, RAX, ret);
+ save_state_ops->set_reg(io_smi, SMM_RAX, ret);
}
static void southbridge_smi_store(
- const struct smm_save_state_ops *save_state_ops)
+ const struct intel_smm_save_state_ops *save_state_ops)
{
u8 sub_command, ret;
void *io_smi;
@@ -307,14 +307,14 @@
if (!io_smi)
return;
/* Command and return value in EAX */
- sub_command = (save_state_ops->get_reg(io_smi, RAX) >> 8) & 0xff;
+ sub_command = (save_state_ops->get_reg(io_smi, SMM_RAX) >> 8) & 0xff;
/* Parameter buffer in EBX */
- reg_ebx = save_state_ops->get_reg(io_smi, RBX);
+ reg_ebx = save_state_ops->get_reg(io_smi, SMM_RBX);
/* drivers/smmstore/smi.c */
ret = smmstore_exec(sub_command, (void *)reg_ebx);
- save_state_ops->set_reg(io_smi, RAX, ret);
+ save_state_ops->set_reg(io_smi, SMM_RAX, ret);
}
static void finalize(void)
@@ -336,7 +336,7 @@
}
void smihandler_southbridge_apmc(
- const struct smm_save_state_ops *save_state_ops)
+ const struct intel_smm_save_state_ops *save_state_ops)
{
uint8_t reg8;
void *state = NULL;
@@ -379,7 +379,7 @@
state = find_save_state(save_state_ops, reg8);
if (state) {
/* EBX in the state save contains the GNVS pointer */
- uint32_t reg_ebx = save_state_ops->get_reg(state, RBX);
+ uint32_t reg_ebx = save_state_ops->get_reg(state, SMM_RBX);
gnvs = (struct global_nvs_t *)(uintptr_t)reg_ebx;
smm_initialized = 1;
printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs);
@@ -402,7 +402,7 @@
}
void smihandler_southbridge_pm1(
- const struct smm_save_state_ops *save_state_ops)
+ const struct intel_smm_save_state_ops *save_state_ops)
{
uint16_t pm1_sts = pmc_clear_pm1_status();
u16 pm1_en = pmc_read_pm1_enable();
@@ -420,13 +420,13 @@
}
void smihandler_southbridge_gpe0(
- const struct smm_save_state_ops *save_state_ops)
+ const struct intel_smm_save_state_ops *save_state_ops)
{
pmc_clear_all_gpe_status();
}
void smihandler_southbridge_tco(
- const struct smm_save_state_ops *save_state_ops)
+ const struct intel_smm_save_state_ops *save_state_ops)
{
uint32_t tco_sts = pmc_clear_tco_status();
@@ -443,7 +443,7 @@
}
void smihandler_southbridge_periodic(
- const struct smm_save_state_ops *save_state_ops)
+ const struct intel_smm_save_state_ops *save_state_ops)
{
uint32_t reg32;
@@ -456,7 +456,7 @@
}
void smihandler_southbridge_gpi(
- const struct smm_save_state_ops *save_state_ops)
+ const struct intel_smm_save_state_ops *save_state_ops)
{
struct gpi_status smi_sts;
@@ -468,7 +468,7 @@
}
void smihandler_southbridge_espi(
- const struct smm_save_state_ops *save_state_ops)
+ const struct intel_smm_save_state_ops *save_state_ops)
{
mainboard_smi_espi_handler();
}
@@ -477,7 +477,7 @@
{
int i;
uint32_t smi_sts;
- const struct smm_save_state_ops *save_state_ops;
+ const struct intel_smm_save_state_ops *save_state_ops;
/*
* We need to clear the SMI status registers, or we won't see what's
@@ -519,22 +519,22 @@
return smm_state->io_misc_info;
}
-static uint64_t em64t100_smm_save_state_get_reg(void *state, enum smm_reg reg)
+static uint64_t em64t100_smm_save_state_get_reg(void *state, enum intel_smm_reg reg)
{
uintptr_t value = 0;
em64t100_smm_state_save_area_t *smm_state = state;
switch (reg) {
- case RAX:
+ case SMM_RAX:
value = smm_state->rax;
break;
- case RBX:
+ case SMM_RBX:
value = smm_state->rbx;
break;
- case RCX:
+ case SMM_RCX:
value = smm_state->rcx;
break;
- case RDX:
+ case SMM_RDX:
value = smm_state->rdx;
break;
default:
@@ -543,21 +543,21 @@
return value;
}
-static void em64t100_smm_save_state_set_reg(void *state, enum smm_reg reg,
+static void em64t100_smm_save_state_set_reg(void *state, enum intel_smm_reg reg,
uint64_t val)
{
em64t100_smm_state_save_area_t *smm_state = state;
switch (reg) {
- case RAX:
+ case SMM_RAX:
smm_state->rax = val;
break;
- case RBX:
+ case SMM_RBX:
smm_state->rbx = val;
break;
- case RCX:
+ case SMM_RCX:
smm_state->rcx = val;
break;
- case RDX:
+ case SMM_RDX:
smm_state->rdx = val;
break;
default:
@@ -571,22 +571,22 @@
return smm_state->io_misc_info;
}
-static uint64_t em64t101_smm_save_state_get_reg(void *state, enum smm_reg reg)
+static uint64_t em64t101_smm_save_state_get_reg(void *state, enum intel_smm_reg reg)
{
uintptr_t value = 0;
em64t101_smm_state_save_area_t *smm_state = state;
switch (reg) {
- case RAX:
+ case SMM_RAX:
value = smm_state->rax;
break;
- case RBX:
+ case SMM_RBX:
value = smm_state->rbx;
break;
- case RCX:
+ case SMM_RCX:
value = smm_state->rcx;
break;
- case RDX:
+ case SMM_RDX:
value = smm_state->rdx;
break;
default:
@@ -595,21 +595,21 @@
return value;
}
-static void em64t101_smm_save_state_set_reg(void *state, enum smm_reg reg,
+static void em64t101_smm_save_state_set_reg(void *state, enum intel_smm_reg reg,
uint64_t val)
{
em64t101_smm_state_save_area_t *smm_state = state;
switch (reg) {
- case RAX:
+ case SMM_RAX:
smm_state->rax = val;
break;
- case RBX:
+ case SMM_RBX:
smm_state->rbx = val;
break;
- case RCX:
+ case SMM_RCX:
smm_state->rcx = val;
break;
- case RDX:
+ case SMM_RDX:
smm_state->rdx = val;
break;
default:
@@ -617,13 +617,13 @@
}
}
-const struct smm_save_state_ops em64t100_smm_ops = {
+const struct intel_smm_save_state_ops em64t100_smm_ops = {
.get_io_misc_info = em64t100_smm_save_state_get_io_misc_info,
.get_reg = em64t100_smm_save_state_get_reg,
.set_reg = em64t100_smm_save_state_set_reg,
};
-const struct smm_save_state_ops em64t101_smm_ops = {
+const struct intel_smm_save_state_ops em64t101_smm_ops = {
.get_io_misc_info = em64t101_smm_save_state_get_io_misc_info,
.get_reg = em64t101_smm_save_state_get_reg,
.set_reg = em64t101_smm_save_state_set_reg,
diff --git a/src/soc/intel/common/block/smm/smitraphandler.c b/src/soc/intel/common/block/smm/smitraphandler.c
index 974c489..b7e25e4 100644
--- a/src/soc/intel/common/block/smm/smitraphandler.c
+++ b/src/soc/intel/common/block/smm/smitraphandler.c
@@ -56,7 +56,7 @@
}
void smihandler_southbridge_mc(
- const struct smm_save_state_ops *save_state_ops)
+ const struct intel_smm_save_state_ops *save_state_ops)
{
u32 reg32 = inl(ACPI_BASE_ADDRESS + SMI_EN);
@@ -68,7 +68,7 @@
}
void smihandler_southbridge_monitor(
- const struct smm_save_state_ops *save_state_ops)
+ const struct intel_smm_save_state_ops *save_state_ops)
{
#define IOTRAP(x) (trap_sts & (1 << x))
u32 trap_cycle;
diff --git a/src/soc/intel/icelake/smihandler.c b/src/soc/intel/icelake/smihandler.c
index b7c37d4..039900e 100644
--- a/src/soc/intel/icelake/smihandler.c
+++ b/src/soc/intel/icelake/smihandler.c
@@ -29,7 +29,7 @@
#define CSME0_BAR 0x0
#define CSME0_FID 0xb0
-const struct smm_save_state_ops *get_smm_save_state_ops(void)
+const struct intel_smm_save_state_ops *get_smm_save_state_ops(void)
{
return &em64t101_smm_ops;
}
diff --git a/src/soc/intel/skylake/smihandler.c b/src/soc/intel/skylake/smihandler.c
index 2e93075..50a82f9 100644
--- a/src/soc/intel/skylake/smihandler.c
+++ b/src/soc/intel/skylake/smihandler.c
@@ -20,7 +20,7 @@
#include <intelblocks/smihandler.h>
#include <soc/pm.h>
-const struct smm_save_state_ops *get_smm_save_state_ops(void)
+const struct intel_smm_save_state_ops *get_smm_save_state_ops(void)
{
return &em64t101_smm_ops;
}
diff --git a/src/soc/intel/tigerlake/smihandler.c b/src/soc/intel/tigerlake/smihandler.c
index bf07bea..25bdacc 100644
--- a/src/soc/intel/tigerlake/smihandler.c
+++ b/src/soc/intel/tigerlake/smihandler.c
@@ -29,7 +29,7 @@
#define CSME0_BAR 0x0
#define CSME0_FID 0xb0
-const struct smm_save_state_ops *get_smm_save_state_ops(void)
+const struct intel_smm_save_state_ops *get_smm_save_state_ops(void)
{
return &em64t101_smm_ops;
}
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