[coreboot-gerrit] Change in coreboot[master]: nb/amd/pi/00730F01: enable ACS and AER for PCIe ports

[Paul Menzel (Code Review)]

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35313 )

Change subject: nb/amd/pi/00730F01: enable ACS and AER for PCIe ports
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Patch Set 7:

(2 comments)

https://review.coreboot.org/c/coreboot/+/35313/7/src/northbridge/amd/pi/0073... 
File src/northbridge/amd/pi/00730F01/northbridge.c:

https://review.coreboot.org/c/coreboot/+/35313/7/src/northbridge/amd/pi/0073... 
PS7, Line 784: result
> ACS is Access Control Services, which is plural. […]

You are right. Sorry.

https://review.coreboot.org/c/coreboot/+/35313/7/src/northbridge/amd/pi/0073... 
PS7, Line 794: 	value |= (BIT(5) | BIT(6));
> AMD BKDG doesn't describe these bits, so I don't know which one is which. This is a 50/50 gamble.

But you write `AER (bit 5)` explicitly. What am I missing?