Jamie Ryu has uploaded this change for review.

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[WIP] mb/google/volteer: Update flashmap descriptor to add RW_UCODE_STAGED

This adds RW_UCODE_STAGED to flashmap descriptor to enable microcode
update.

BUG=b:149547271
TEST=Build and boot volteer2 to OS

Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Change-Id: I0af7469cc2767cdf5933e65f81686f9edbfa830d
---
M src/mainboard/google/volteer/chromeos.fmd
1 file changed, 8 insertions(+), 7 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/46622/1

diff --git a/src/mainboard/google/volteer/chromeos.fmd b/src/mainboard/google/volteer/chromeos.fmd
index 07a5464..dc0aa9d 100644
--- a/src/mainboard/google/volteer/chromeos.fmd
+++ b/src/mainboard/google/volteer/chromeos.fmd
@@ -8,17 +8,17 @@
 		# of BIOS regions start at 16MiB boundary. Since this is a 32MiB
 		# SPI flash only the top 16MiB actually gets memory mapped.
 		RW_LEGACY(CBFS)@0x0 0xb00000
-		RW_SECTION_A@0xb00000 0x5e0000 {
+		RW_SECTION_A@0xb00000 0x5c0000 {
 			VBLOCK_A@0x0 0x10000
-			FW_MAIN_A(CBFS)@0x10000 0x5cffc0
-			RW_FWID_A@0x5dffc0 0x40
+			FW_MAIN_A(CBFS)@0x10000 0x5affc0
+			RW_FWID_A@0x5bffc0 0x40
 		}
-		RW_SECTION_B@0x10e0000 0x5e0000 {
+		RW_SECTION_B@0x10c0000 0x5c0000 {
 			VBLOCK_B@0x0 0x10000
-			FW_MAIN_B(CBFS)@0x10000 0x5cffc0
-			RW_FWID_B@0x5dffc0 0x40
+			FW_MAIN_B(CBFS)@0x10000 0x5affc0
+			RW_FWID_B@0x5bffc0 0x40
 		}
-		RW_MISC@0x16c0000 0x40000 {
+		RW_MISC@0x1680000 0x80000 {
 			UNIFIED_MRC_CACHE(PRESERVE)@0x0 0x30000 {
 				RECOVERY_MRC_CACHE@0x0 0x10000
 				RW_MRC_CACHE@0x10000 0x20000
@@ -30,6 +30,7 @@
 			}
 			RW_VPD(PRESERVE)@0x38000 0x2000
 			RW_NVRAM(PRESERVE)@0x3a000 0x6000
+			RW_UCODE_STAGED@0x40000 0x40000
 		}
 		# Make WP_RO region align with SPI vendor
 		# memory protected range specification.

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