Attention is currently required from: Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Shuo Liu, Tim Chu.
Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85319?usp=email )
Change subject: soc/intel/xeon_sp: Advertise DIMMs on skylake_sp as well ......................................................................
soc/intel/xeon_sp: Advertise DIMMs on skylake_sp as well
Add the MEMMAP_DIMM_DEVICE_INFO_STRUCT for skylake_sp and let common code fill in the SMBIOS type 17 entries for all slots and found DIMMs.
This also allows to build dimm.c unconditionally on all xeon_sp socs.
Test: On ocp/tiogapass all DIMMs and slots are visible in SMBIOS.
Change-Id: I686b1e3ef946240785111f86a5f23a109a6a52ad Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com --- M src/soc/intel/xeon_sp/Makefile.mk M src/soc/intel/xeon_sp/cpx/Makefile.mk M src/soc/intel/xeon_sp/gnr/Makefile.mk M src/soc/intel/xeon_sp/skx/romstage.c M src/soc/intel/xeon_sp/spr/Makefile.mk M src/vendorcode/intel/fsp/fsp2_0/skylake_sp/hob_memmap.h 6 files changed, 73 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/85319/1
diff --git a/src/soc/intel/xeon_sp/Makefile.mk b/src/soc/intel/xeon_sp/Makefile.mk index e44f809..711fd49 100644 --- a/src/soc/intel/xeon_sp/Makefile.mk +++ b/src/soc/intel/xeon_sp/Makefile.mk @@ -10,6 +10,7 @@ bootblock-y += bootblock.c spi.c lpc.c pch.c report_platform.c romstage-y += romstage.c reset.c util.c spi.c pmutil.c memmap.c ddr.c romstage-y += config.c +romstage-y += dimm.c romstage-y += ../../../cpu/intel/car/romstage.c ramstage-y += uncore.c reset.c util.c lpc.c spi.c ramstage.c chip_common.c ramstage-y += memmap.c pch.c lockdown.c finalize.c diff --git a/src/soc/intel/xeon_sp/cpx/Makefile.mk b/src/soc/intel/xeon_sp/cpx/Makefile.mk index a24b50e..b54b0ef 100644 --- a/src/soc/intel/xeon_sp/cpx/Makefile.mk +++ b/src/soc/intel/xeon_sp/cpx/Makefile.mk @@ -6,7 +6,6 @@ subdirs-y += ../../../../cpu/intel/microcode
romstage-y += romstage.c soc_util.c -romstage-y += ../dimm.c romstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c romstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c
diff --git a/src/soc/intel/xeon_sp/gnr/Makefile.mk b/src/soc/intel/xeon_sp/gnr/Makefile.mk index 9b07408..054d513 100644 --- a/src/soc/intel/xeon_sp/gnr/Makefile.mk +++ b/src/soc/intel/xeon_sp/gnr/Makefile.mk @@ -12,7 +12,6 @@ romstage-y += romstage.c romstage-y += soc_util.c romstage-y += soc_iio.c -romstage-y += ../dimm.c romstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c
ramstage-y += chip.c diff --git a/src/soc/intel/xeon_sp/skx/romstage.c b/src/soc/intel/xeon_sp/skx/romstage.c index 21b3522..f66022d 100644 --- a/src/soc/intel/xeon_sp/skx/romstage.c +++ b/src/soc/intel/xeon_sp/skx/romstage.c @@ -26,4 +26,37 @@ m_cfg->VTdConfig.ATS = config->ats_support; }
-void save_dimm_info(void) {} +uint8_t get_error_correction_type(const uint8_t RasModesEnabled) +{ + switch (RasModesEnabled) { + case CH_INDEPENDENT: + return MEMORY_ARRAY_ECC_SINGLE_BIT; + case FULL_MIRROR_1LM: + case PARTIAL_MIRROR_1LM: + case FULL_MIRROR_2LM: + case PARTIAL_MIRROR_2LM: + return MEMORY_ARRAY_ECC_MULTI_BIT; + case RK_SPARE: + return MEMORY_ARRAY_ECC_SINGLE_BIT; + case CH_LOCKSTEP: + return MEMORY_ARRAY_ECC_SINGLE_BIT; + default: + return MEMORY_ARRAY_ECC_MULTI_BIT; + } +} + +uint32_t get_max_capacity_mib(void) +{ + /* According to Dear Customer Letter it's 1.12 TB per processor. */ + return 1.12 * MiB * CONFIG_MAX_SOCKET; +} + +uint8_t get_max_dimm_count(void) +{ + return MAX_DIMM; +} + +uint8_t get_dram_type(const struct SystemMemoryMapHob *hob) +{ + return MEMORY_TYPE_DDR4; +} diff --git a/src/soc/intel/xeon_sp/spr/Makefile.mk b/src/soc/intel/xeon_sp/spr/Makefile.mk index c5f9ece..f1755e4 100644 --- a/src/soc/intel/xeon_sp/spr/Makefile.mk +++ b/src/soc/intel/xeon_sp/spr/Makefile.mk @@ -9,7 +9,6 @@ subdirs-y += ../../../../cpu/intel/microcode
romstage-y += romstage.c soc_util.c -romstage-y += ../dimm.c romstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c romstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c
diff --git a/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/hob_memmap.h b/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/hob_memmap.h index f97056a..5a1b2f2 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/hob_memmap.h +++ b/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/hob_memmap.h @@ -36,6 +36,15 @@ 0xbd, 0x56, 0xda, 0x91, 0xc0, 0x7f \ }
+#define CH_INDEPENDENT 0 +#define FULL_MIRROR_1LM BIT0 +#define FULL_MIRROR_2LM BIT1 +#define CH_LOCKSTEP BIT2 +#define RK_SPARE BIT3 +#define PARTIAL_MIRROR_1LM BIT5 +#define PARTIAL_MIRROR_2LM BIT6 +#define STAT_VIRT_LOCKSTEP BIT7 + #define MEMTYPE_1LM_MASK (1 << 0) #define MEMTYPE_2LM_MASK (1 << 1) #define MEMTYPE_VOLATILE_MASK (MEMTYPE_1LM_MASK | MEMTYPE_2LM_MASK) @@ -50,6 +59,34 @@
#pragma pack(1)
+typedef struct DimmDevice { + UINT8 Present; + UINT8 reserved1[3]; + UINT8 NumRanks; + UINT8 reserved2[1]; + UINT8 actKeyByte2; + UINT8 reserved3[9]; + UINT16 DimmSize; + UINT8 reserved4[8]; + UINT16 VendorID; + UINT16 DeviceID; + UINT8 reserved5[24]; + UINT8 serialNumber[4]; + UINT8 PartNumber[4]; + UINT8 reserved6[50]; + INT32 commonTck; + UINT8 reserved7[24]; +} MEMMAP_DIMM_DEVICE_INFO_STRUCT; + +struct ChannelDevice { + UINT8 reserved1[191]; + MEMMAP_DIMM_DEVICE_INFO_STRUCT DimmInfo[MAX_IMC]; +}; +typedef struct socket { + UINT8 reserved[2075]; + struct ChannelDevice ChannelInfo[MAX_CH]; +} MEMMAP_SOCKET; + struct SystemMemoryMapElement { UINT8 NodeId; // Node ID of the HA Owning the memory UINT8 SocketId; // Socket Id of socket that has his memory - ONLY IN NUMA @@ -98,7 +135,7 @@ UINT8 maxCh; struct SystemMemoryMapElement Element[MAX_SOCKET * SAD_RULES]; UINT8 reserved1[982]; - UINT8 reserved2[4901*MAX_SOCKET]; + MEMMAP_SOCKET Socket[MAX_SOCKET]; UINT8 reserved3[707]; };