[coreboot-gerrit] Change in ...coreboot[master]: soc/intel/icelake: Make correct C-state entries for S0ix and non-S0ix

[Subrata Banik (Code Review)]

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31153

Change subject: soc/intel/icelake: Make correct C-state entries for S0ix and non-S0ix
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soc/intel/icelake: Make correct C-state entries for S0ix and non-S0ix

TEST=Dump SSDT entries to verify _CST between S0ix enable and disable.

Change-Id: I82d8bf9d143263a80a544f6e11186a3bc9c41052
Signed-off-by: Subrata Banik 
---
M src/soc/intel/icelake/acpi.c
1 file changed, 2 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/31153/1

diff --git a/src/soc/intel/icelake/acpi.c b/src/soc/intel/icelake/acpi.c
index 39ec58a..0e13d034 100644
--- a/src/soc/intel/icelake/acpi.c
+++ b/src/soc/intel/icelake/acpi.c
@@ -119,13 +119,13 @@
    },
 };

-static int cstate_set_s0ix[] = {
+static int cstate_set_non_s0ix[] = {
    C_STATE_C1E,
    C_STATE_C6_LONG_LAT,
    C_STATE_C7S_LONG_LAT
 };

-static int cstate_set_non_s0ix[] = {
+static int cstate_set_s0ix[] = {
    C_STATE_C1E,
    C_STATE_C7S_LONG_LAT,
    C_STATE_C10