[coreboot-gerrit] Patch set updated for coreboot: caa0f7d exynos5420: set L2ACTLR parameters for A15 cores

[Patrick Georgi]

Patrick Georgi ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4441

-gerrit

commit caa0f7d56bee6765c90b0739bc0bb349a9616f59
Author: David Hendricks 
Date:   Tue Aug 6 18:05:55 2013 -0700

exynos5420: set L2ACTLR parameters for A15 cores

This patch does the following for the A15 cores:
    - Disable clean/evict push to external
    - Enable hazard detect timout
    - Prevent gating the L2 logic clock

This is ported from https://gerrit.chromium.org/gerrit/#/c/60154

Signed-off-by: David Hendricks

Change-Id: I7ac9f40acecfa7daee6fb81772676bf5119d0536
    Reviewed-on: https://gerrit.chromium.org/gerrit/64862
    Commit-Queue: David Hendricks 
    Reviewed-by: David Hendricks 
    Tested-by: David Hendricks 
---
 src/cpu/samsung/exynos5420/cpu.c | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/src/cpu/samsung/exynos5420/cpu.c b/src/cpu/samsung/exynos5420/cpu.c
index 1940b88..bda46de 100644
--- a/src/cpu/samsung/exynos5420/cpu.c
+++ b/src/cpu/samsung/exynos5420/cpu.c
@@ -198,4 +198,20 @@ void exynos5420_config_l2_cache(void)
     */
    val = (1 << 9) | (0x2 << 6) | (1 << 5) | (0x2);
    write_l2ctlr(val);
+
+	val = read_l2actlr();
+
+	/* L2ACTLR[3]: Disable clean/evict push to external */
+	val |= (1 << 3);
+
+	/* L2ACTLR[7]: Enable hazard detect timeout for A15 */
+	val |= (1 << 7);
+
+	/* L2ACTLR[27]: Prevents stopping the L2 logic clock */
+	val |= (1 << 27);
+
+	write_l2actlr(val);
+
+	/* Read the l2 control register to force things to take effect? */
+	val = read_l2ctlr();
 }