Subrata Banik has uploaded this change for review.
soc/intel/common/systemagent: Add SOC_INTEL_COMMON_BLOCK_SA_VERSION_2
System Agent (SA) register 0x60:PCIEXBAR register LENGTH offset definition has
been changed for newer SoC. This change provides a new Kconfig option that
can be selected by SoCs using these new bit definitions of LENGTH. Common code
takes care of setting the right value for pciex length depending upon the version
selected by SOC.
TEST=DSDT dump shows PCIEXBAR.LENGTH offset (3:1) for TGL
Change-Id: Ifa00c4e6b872896ace975f1c6bd56c6efb172410
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
---
M src/soc/intel/common/block/acpi/acpi/northbridge.asl
M src/soc/intel/common/block/systemagent/Kconfig
M src/soc/intel/common/block/systemagent/systemagent_def.h
M src/soc/intel/common/block/systemagent/systemagent_early.c
4 files changed, 62 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/38456/1
diff --git a/src/soc/intel/common/block/acpi/acpi/northbridge.asl b/src/soc/intel/common/block/acpi/acpi/northbridge.asl
index d271dda..ac9e843 100644
--- a/src/soc/intel/common/block/acpi/acpi/northbridge.asl
+++ b/src/soc/intel/common/block/acpi/acpi/northbridge.asl
@@ -40,8 +40,13 @@
Offset(0x60), /* PCIEXBAR (0:0:0:60) */
PXEN, 1, /* Enable */
- PXSZ, 2, /* PCI Express Size */
+#if CONFIG(SOC_INTEL_COMMON_BLOCK_SA_VERSION_2)
+ PXSZ, 3, /* PCI Express Size */
+ , 22,
+#else
+ PXSZ, 2, /* PCI Express Size */
, 23,
+#endif
PXBR, 6, /* PCI Express BAR [31:26] */
Offset(0x68), /* DMIBAR (0:0:0:68) */
@@ -241,7 +246,15 @@
/* Get PCIe Length */
Method (GPCL, 0, Serialized)
{
+#if CONFIG(SOC_INTEL_COMMON_BLOCK_SA_VERSION_2)
+ If (LLess (\_SB.PCI0.MCHC.PXSZ, 3)) {
+ ShiftRight (0x10000000, \_SB.PCI0.MCHC.PXSZ, Local0)
+ } Else {
+ Store(0x10000000, Local0)
+ }
+#else
ShiftRight (0x10000000, \_SB.PCI0.MCHC.PXSZ, Local0)
+#endif
Return (Local0)
}
diff --git a/src/soc/intel/common/block/systemagent/Kconfig b/src/soc/intel/common/block/systemagent/Kconfig
index 1222573..017d85e 100644
--- a/src/soc/intel/common/block/systemagent/Kconfig
+++ b/src/soc/intel/common/block/systemagent/Kconfig
@@ -3,12 +3,24 @@
help
Intel Processor common System Agent support
+config SOC_INTEL_COMMON_BLOCK_SA_VERSION_2
+ bool
+ default n
+ select SOC_INTEL_COMMON_BLOCK_SA
+ help
+ Intel Processor Common System Agent support version 2 to handle
+ DRAM changes introduced in TGL.
+
config MMCONF_BASE_ADDRESS
hex
default 0xe0000000
config SA_PCIEX_LENGTH
hex
+ default 0x100000000 if (PCIEX_LENGTH_4096MB)
+ default 0x80000000 if (PCIEX_LENGTH_2048MB)
+ default 0x40000000 if (PCIEX_LENGTH_1024MB)
+ default 0x20000000 if (PCIEX_LENGTH_512MB)
default 0x10000000 if (PCIEX_LENGTH_256MB)
default 0x8000000 if (PCIEX_LENGTH_128MB)
default 0x4000000 if (PCIEX_LENGTH_64MB)
@@ -16,6 +28,22 @@
help
This option allows you to select length of PCIEX region.
+if SOC_INTEL_COMMON_BLOCK_SA_VERSION_2
+
+config PCIEX_LENGTH_4096MB
+ bool
+
+config PCIEX_LENGTH_2048MB
+ bool
+
+config PCIEX_LENGTH_1024MB
+ bool
+
+config PCIEX_LENGTH_512MB
+ bool
+
+endif
+
config PCIEX_LENGTH_256MB
bool
diff --git a/src/soc/intel/common/block/systemagent/systemagent_def.h b/src/soc/intel/common/block/systemagent/systemagent_def.h
index b89a10d..5f54c72 100644
--- a/src/soc/intel/common/block/systemagent/systemagent_def.h
+++ b/src/soc/intel/common/block/systemagent/systemagent_def.h
@@ -31,6 +31,12 @@
#define DPR_PRS (1 << 1)
#define DPR_SIZE_MASK 0xff0
+#if CONFIG(SOC_INTEL_COMMON_BLOCK_SA_VERSION_2)
+#define PCIEXBAR_LENGTH_4096MB 6
+#define PCIEXBAR_LENGTH_2048MB 5
+#define PCIEXBAR_LENGTH_1024MB 4
+#define PCIEXBAR_LENGTH_512MB 3
+#endif
#define PCIEXBAR_LENGTH_64MB 2
#define PCIEXBAR_LENGTH_128MB 1
#define PCIEXBAR_LENGTH_256MB 0
diff --git a/src/soc/intel/common/block/systemagent/systemagent_early.c b/src/soc/intel/common/block/systemagent/systemagent_early.c
index d6f129d..f0a867a 100644
--- a/src/soc/intel/common/block/systemagent/systemagent_early.c
+++ b/src/soc/intel/common/block/systemagent/systemagent_early.c
@@ -40,6 +40,20 @@
/* Get PCI Express Region Length */
switch (CONFIG_SA_PCIEX_LENGTH) {
+#if CONFIG(SOC_INTEL_COMMON_BLOCK_SA_VERSION_2)
+ case 4096 * MiB:
+ pciexbar_length = PCIEXBAR_LENGTH_4096MB;
+ break;
+ case 2048 * MiB:
+ pciexbar_length = PCIEXBAR_LENGTH_2048MB;
+ break;
+ case 1024 * MiB:
+ pciexbar_length = PCIEXBAR_LENGTH_1024MB;
+ break;
+ case 512 * MiB:
+ pciexbar_length = PCIEXBAR_LENGTH_512MB;
+ break;
+#endif
case 256 * MiB:
pciexbar_length = PCIEXBAR_LENGTH_256MB;
break;
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