Michael Niewöhner submitted this change.

View Change

soc/samsung/exynos5250: Drop dead code

This code is not even being build-tested. Drop it before it grows moss.

Change-Id: I4772680875b20308e57da073bbcdc4597aeed893
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43215
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
M src/soc/samsung/exynos5250/dmc_init_ddr3.c
M src/soc/samsung/exynos5250/fb.c
M src/soc/samsung/exynos5250/uart.c
3 files changed, 0 insertions(+), 62 deletions(-)

diff --git a/src/soc/samsung/exynos5250/dmc_init_ddr3.c b/src/soc/samsung/exynos5250/dmc_init_ddr3.c
index 029171ef..f415020 100644
--- a/src/soc/samsung/exynos5250/dmc_init_ddr3.c
+++ b/src/soc/samsung/exynos5250/dmc_init_ddr3.c
@@ -19,20 +19,6 @@
 	write32(&exynos_clock->lpddr3phy_ctrl,
 		LPDDR3PHY_CTRL_PHY_RESET_DISABLE);
 
-#if 0
-	/*
-	 * For proper memory initialization there should be a minimum delay of
-	 * 500us after the LPDDR3PHY_CTRL_PHY_RESET signal.
-	 * The below value is an approximate value whose calculation in done
-	 * considering that sdelay takes 2 instruction for every 1 delay cycle.
-	 * And assuming each instruction takes 1 clock cycle i.e 1/(1.7 Ghz)sec
-	 * So for 500 usec, the number of delay cycle should be
-	 * (500 * 10^-6) * (1.7 * 10^9) / 2 = 425000
-	 *
-	 * TODO(hatim.rv@samsung.com): Implement the delay using timer/counter
-	 */
-	sdelay(425000);
-#endif
 	udelay(500);
 }
 
diff --git a/src/soc/samsung/exynos5250/fb.c b/src/soc/samsung/exynos5250/fb.c
index 0292d76..98a4c66 100644
--- a/src/soc/samsung/exynos5250/fb.c
+++ b/src/soc/samsung/exynos5250/fb.c
@@ -140,14 +140,6 @@
 	write32(&exynos_fimd->dpclkcon, 1 << 1);
 }
 
-#ifdef UNUSED_CODE
-void exynos_fimd_disable(void)
-{
-	write32(&exynos_fimd->wincon0, 0);
-	clrbits32(&exynos_fimd->shadowcon, CHANNEL0_EN);
-}
-#endif
-
 /*
  * Configure DP in slave mode and wait for video stream.
  *
diff --git a/src/soc/samsung/exynos5250/uart.c b/src/soc/samsung/exynos5250/uart.c
index b3dd37e..3263125 100644
--- a/src/soc/samsung/exynos5250/uart.c
+++ b/src/soc/samsung/exynos5250/uart.c
@@ -13,34 +13,6 @@
 #define RX_FIFO_FULL_MASK	(1 << 8)
 #define TX_FIFO_FULL_MASK	(1 << 24)
 
-#if 0
-/*
- * The coefficient, used to calculate the baudrate on S5P UARTs is
- * calculated as
- * C = UBRDIV * 16 + number_of_set_bits_in_UDIVSLOT
- * however, section 31.6.11 of the datasheet doesn't recommend using 1 for 1,
- * 3 for 2, ... (2^n - 1) for n, instead, they suggest using these constants:
- */
-static const int udivslot[] = {
-	0,
-	0x0080,
-	0x0808,
-	0x0888,
-	0x2222,
-	0x4924,
-	0x4a52,
-	0x54aa,
-	0x5555,
-	0xd555,
-	0xd5d5,
-	0xddd5,
-	0xdddd,
-	0xdfdd,
-	0xdfdf,
-	0xffdf,
-};
-#endif
-
 static void serial_setbrg_dev(struct s5p_uart *uart)
 {
 	u32 uclk;
@@ -51,18 +23,6 @@
 	val = uclk / get_uart_baudrate();
 
 	write32(&uart->ubrdiv, val / 16 - 1);
-
-	/*
-	 * FIXME(dhendrix): the original uart.h had a "br_rest" value which
-	 * does not seem relevant to the exynos5250... not entirely sure
-	 * where/if we need to worry about it here
-	 */
-#if 0
-	if (s5p_uart_divslot())
-		writel(udivslot[val % 16], &uart->rest.slot);
-	else
-		writeb(val % 16, &uart->rest.value);
-#endif
 }
 
 /*

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