Subrata Banik has uploaded this change for review.
Include required files to compile in postcar to skip ramstage
Change-Id: I5269d562baf8f216e17794ffceb8f97061483515
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
---
M src/arch/x86/Makefile.inc
A src/arch/x86/c_postcar_start.S
M src/arch/x86/exit_car.S
M src/commonlib/Makefile.inc
M src/cpu/intel/microcode/Makefile.inc
M src/cpu/intel/turbo/Makefile.inc
M src/cpu/x86/Makefile.inc
M src/cpu/x86/lapic/Makefile.inc
M src/cpu/x86/mtrr/Makefile.inc
M src/cpu/x86/name/Makefile.inc
M src/cpu/x86/smm/Makefile.inc
M src/device/Makefile.inc
M src/drivers/elog/Makefile.inc
M src/drivers/intel/fsp2_0/Makefile.inc
M src/drivers/intel/fsp2_0/ppi/Makefile.inc
M src/drivers/intel/gma/Makefile.inc
M src/drivers/mrc_cache/Makefile.inc
M src/drivers/pc80/pc/Makefile.inc
M src/ec/google/chromeec/Makefile.inc
M src/lib/Makefile.inc
M src/security/vboot/Makefile.inc
M src/soc/intel/common/Makefile.inc
M src/vendorcode/google/chromeos/Makefile.inc
23 files changed, 378 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/32675/1
diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 6e4ee76..63e84ca 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -283,6 +283,20 @@
postcar-y += postcar.c
postcar-$(CONFIG_COLLECT_TIMESTAMPS_TSC) += timestamp.c
+ifeq ($(CONFIG_SKIP_RAMSTAGE),y)
+postcar-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c
+postcar-$(CONFIG_HAVE_ACPI_TABLES) += acpigen.c
+postcar-$(CONFIG_HAVE_ACPI_TABLES) += acpigen_dsm.c
+postcar-$(CONFIG_HAVE_ACPI_TABLES) += acpi_device.c
+postcar-$(CONFIG_HAVE_ACPI_TABLES) += acpi_pld.c
+postcar-y += c_postcar_start.S
+postcar-y += cpu.c
+postcar-$(CONFIG_IOAPIC) += ioapic.c
+postcar-$(CONFIG_GENERATE_SMBIOS_TABLES) += smbios.c
+postcar-y += tables.c
+postcar-$(CONFIG_HAVE_ACPI_RESUME) += wakeup.S
+endif
+
LDFLAGS_postcar += -Map $(objcbfs)/postcar.map
$(objcbfs)/postcar.debug: $$(postcar-objs)
diff --git a/src/arch/x86/c_postcar_start.S b/src/arch/x86/c_postcar_start.S
new file mode 100644
index 0000000..70c38b5
--- /dev/null
+++ b/src/arch/x86/c_postcar_start.S
@@ -0,0 +1,216 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <cpu/x86/post_code.h>
+
+/* Place the stack in the bss section. It's not necessary to define it in the
+ * the linker script. */
+ .section .bss, "aw", @nobits
+.global _stack
+.global _estack
+
+/* Stack alignment is not enforced with rmodule loader, reserve one
+ * extra CPU such that alignment can be enforced on entry. */
+.align CONFIG_STACK_SIZE
+_stack:
+.space (CONFIG_MAX_CPUS+1)*CONFIG_STACK_SIZE
+_estack:
+#if CONFIG(COOP_MULTITASKING)
+.global thread_stacks
+thread_stacks:
+.space CONFIG_STACK_SIZE*CONFIG_NUM_THREADS
+#endif
+
+ .section ".text._start", "ax", @progbits
+#ifdef __x86_64__
+ .code64
+#else
+ .code32
+#endif
+ .globl cstart
+cstart:
+ cli
+ lgdt %cs:gdtaddr
+#ifndef __x86_64__
+ ljmp $0x10, $1f
+#endif
+1: movl $0x18, %eax
+ movl %eax, %ds
+ movl %eax, %es
+ movl %eax, %ss
+ movl %eax, %fs
+ movl %eax, %gs
+#ifdef __x86_64__
+ mov $0x48, %ecx
+ call SetCodeSelector
+#endif
+
+ post_code(POST_ENTRY_C_START) /* post 13 */
+
+ cld
+
+ /** poison the stack. Code should not count on the
+ * stack being full of zeros. This stack poisoning
+ * recently uncovered a bug in the broadcast SIPI
+ * code.
+ */
+ leal _stack, %edi
+ movl $_estack, %ecx
+ subl %edi, %ecx
+ shrl $2, %ecx /* it is 32 bit aligned, right? */
+ movl $0xDEADBEEF, %eax
+ rep
+ stosl
+
+ /* Set new stack with enforced alignment. */
+ movl $_estack, %esp
+ andl $(~(CONFIG_STACK_SIZE-1)), %esp
+
+#if CONFIG(COOP_MULTITASKING)
+ /* Push the thread pointer. */
+ push $0
+#endif
+ /* Push the CPU index and struct CPU */
+ push $0
+ push $0
+
+ /*
+ * Now we are finished. Memory is up, data is copied and
+ * bss is cleared. Now we call the main routine and
+ * let it do the rest.
+ */
+ post_code(POST_PRE_HARDWAREMAIN) /* post fe */
+
+ andl $0xFFFFFFF0, %esp
+
+ call main
+ /* NOTREACHED */
+.Lhlt:
+ post_code(POST_DEAD_CODE) /* post ee */
+ hlt
+ jmp .Lhlt
+
+ .globl gdt, gdt_end
+
+gdtaddr:
+ .word gdt_end - gdt - 1
+#ifdef __x86_64__
+ .quad gdt
+#else
+ .long gdt /* we know the offset */
+#endif
+
+ .data
+
+ /* This is the gdt for GCC part of coreboot.
+ * It is different from the gdt in ROMCC/ASM part of coreboot
+ * which is defined in entry32.inc
+ *
+ * When the machine is initially started, we use a very simple
+ * gdt from ROM (that in entry32.inc) which only contains those
+ * entries we need for protected mode.
+ *
+ * When we're executing code from RAM, we want to do more complex
+ * stuff, like initializing PCI option ROMs in real mode, or doing
+ * a resume from a suspend to RAM.
+ */
+gdt:
+ /* selgdt 0, unused */
+ .word 0x0000, 0x0000 /* dummy */
+ .byte 0x00, 0x00, 0x00, 0x00
+
+ /* selgdt 8, unused */
+ .word 0x0000, 0x0000 /* dummy */
+ .byte 0x00, 0x00, 0x00, 0x00
+
+ /* selgdt 0x10, flat code segment */
+ .word 0xffff, 0x0000
+ .byte 0x00, 0x9b, 0xcf, 0x00 /* G=1 and 0x0f, So we get 4Gbytes for
+ * limit
+ */
+
+ /* selgdt 0x18, flat data segment */
+ .word 0xffff, 0x0000
+#ifdef __x86_64__
+ .byte 0x00, 0x92, 0xcf, 0x00
+#else
+ .byte 0x00, 0x93, 0xcf, 0x00
+#endif
+
+ /* selgdt 0x20, unused */
+ .word 0x0000, 0x0000 /* dummy */
+ .byte 0x00, 0x00, 0x00, 0x00
+
+ /* The next two entries are used for executing VGA option ROMs */
+
+ /* selgdt 0x28 16 bit 64k code at 0x00000000 */
+ .word 0xffff, 0x0000
+ .byte 0, 0x9a, 0, 0
+
+ /* selgdt 0x30 16 bit 64k data at 0x00000000 */
+ .word 0xffff, 0x0000
+ .byte 0, 0x92, 0, 0
+
+ /* The next two entries are used for ACPI S3 RESUME */
+
+ /* selgdt 0x38, flat data segment 16 bit */
+ .word 0x0000, 0x0000 /* dummy */
+ .byte 0x00, 0x93, 0x8f, 0x00 /* G=1 and 0x0f, So we get 4Gbytes for
+ * limit
+ */
+
+ /* selgdt 0x40, flat code segment 16 bit */
+ .word 0xffff, 0x0000
+ .byte 0x00, 0x9b, 0x8f, 0x00 /* G=1 and 0x0f, So we get 4Gbytes for
+ * limit
+ */
+
+#ifdef __x86_64__
+ /* selgdt 0x48, flat x64 code segment */
+ .word 0xffff, 0x0000
+ .byte 0x00, 0x9b, 0xaf, 0x00
+#endif
+gdt_end:
+
+ .section ".text._start", "ax", @progbits
+#ifdef __x86_64__
+SetCodeSelector:
+ # save rsp because iret will align it to a 16 byte boundary
+ mov %rsp, %rdx
+
+ # use iret to jump to a 64-bit offset in a new code segment
+ # iret will pop cs:rip, flags, then ss:rsp
+ mov %ss, %ax # need to push ss..
+ push %rax # push ss instuction not valid in x64 mode,
+ # so use ax
+ push %rsp
+ pushfq
+ push %rcx # cx is code segment selector from caller
+ mov $setCodeSelectorLongJump, %rax
+ push %rax
+
+ # the iret will continue at next instruction, with the new cs value
+ # loaded
+ iretq
+
+setCodeSelectorLongJump:
+ # restore rsp, it might not have been 16-byte aligned on entry
+ mov %rdx, %rsp
+ ret
+
+ .previous
+.code64
+#else
+ .previous
+.code32
+#endif
diff --git a/src/arch/x86/exit_car.S b/src/arch/x86/exit_car.S
index 769a758..234c716 100644
--- a/src/arch/x86/exit_car.S
+++ b/src/arch/x86/exit_car.S
@@ -126,6 +126,9 @@
/* Align stack to 16 bytes at call instruction. */
andl $0xfffffff0, %esp
+#if CONFIG(SKIP_RAMSTAGE)
+ call cstart
+#endif
/* Call into main for postcar. */
call main
/* Should never return. */
diff --git a/src/commonlib/Makefile.inc b/src/commonlib/Makefile.inc
index b6e8913..1865be5 100644
--- a/src/commonlib/Makefile.inc
+++ b/src/commonlib/Makefile.inc
@@ -38,3 +38,8 @@
postcar-y += lz4_wrapper.c
ramstage-y += sort.c
+
+ifeq ($(CONFIG_SKIP_RAMSTAGE),y)
+postcar-$(CONFIG_PLATFORM_USES_FSP2_0) += fsp_relocate.c
+postcar-y += sort.c
+endif
diff --git a/src/cpu/intel/microcode/Makefile.inc b/src/cpu/intel/microcode/Makefile.inc
index 2df1d5e..922d340 100644
--- a/src/cpu/intel/microcode/Makefile.inc
+++ b/src/cpu/intel/microcode/Makefile.inc
@@ -3,3 +3,6 @@
ramstage-$(CONFIG_SUPPORT_CPU_UCODE_IN_CBFS) += microcode.c
romstage-$(CONFIG_SUPPORT_CPU_UCODE_IN_CBFS) += microcode.c
+ifeq ($(CONFIG_SKIP_RAMSTAGE),y)
+postcar-$(CONFIG_SUPPORT_CPU_UCODE_IN_CBFS) += microcode.c
+endif
\ No newline at end of file
diff --git a/src/cpu/intel/turbo/Makefile.inc b/src/cpu/intel/turbo/Makefile.inc
index 48ec55d..68b46c7 100644
--- a/src/cpu/intel/turbo/Makefile.inc
+++ b/src/cpu/intel/turbo/Makefile.inc
@@ -1 +1,2 @@
+postcar-$(CONFIG_SKIP_RAMSTAGE) += turbo.c
ramstage-y += turbo.c
diff --git a/src/cpu/x86/Makefile.inc b/src/cpu/x86/Makefile.inc
index 3e8a664..e68f21e 100644
--- a/src/cpu/x86/Makefile.inc
+++ b/src/cpu/x86/Makefile.inc
@@ -37,3 +37,29 @@
$(call src-to-obj,ramstage,$(SIPI_BIN).manual): $(SIPI_BIN)
@printf " OBJCOPY $(subst $(obj)/,,$(@))\n"
cd $(dir $<); $(OBJCOPY_rmodules_$(ARCH-ramstage-y)) -I binary $(notdir $<) $(target-objcopy) $(abspath $@)
+
+ifeq ($(CONFIG_SKIP_RAMSTAGE),y)
+postcar-$(CONFIG_PARALLEL_MP) += mp_init.c
+postcar-y += backup_default_smm.c
+
+ifeq ($(CONFIG_PARALLEL_MP),y)
+postcar-srcs += $(SIPI_BIN).manual
+endif
+rmodules_$(ARCH-postcar-y)-$(CONFIG_PARALLEL_MP) += sipi_vector.S
+
+$(SIPI_DOTO): $(call src-to-obj,rmodules_$(ARCH-postcar-y),src/cpu/x86/sipi_vector.S)
+ $(CC_rmodules_$(ARCH-postcar-y)) $(CFLAGS_rmodules_$(ARCH-postcar-y)) -nostdlib -r -o $@ $^
+
+ifeq ($(CONFIG_ARCH_POSTCAR_X86_32),y)
+$(eval $(call rmodule_link,$(SIPI_ELF), $(SIPI_DOTO), 0,x86_32))
+else
+$(eval $(call rmodule_link,$(SIPI_ELF), $(SIPI_DOTO), 0,x86_64))
+endif
+
+$(SIPI_BIN): $(SIPI_RMOD)
+ $(OBJCOPY_postcar) -O binary $< $@
+
+$(call src-to-obj,postcar,$(SIPI_BIN).manual): $(SIPI_BIN)
+ @printf " OBJCOPY $(subst $(obj)/,,$(@))\n"
+ cd $(dir $<); $(OBJCOPY_rmodules_$(ARCH-postcar-y)) -I binary $(notdir $<) $(target-objcopy) $(abspath $@)
+endif
diff --git a/src/cpu/x86/lapic/Makefile.inc b/src/cpu/x86/lapic/Makefile.inc
index 9454f8f..a6a59c7 100644
--- a/src/cpu/x86/lapic/Makefile.inc
+++ b/src/cpu/x86/lapic/Makefile.inc
@@ -1,4 +1,5 @@
ramstage-y += lapic.c
+postcar-$(CONFIG_SKIP_RAMSTAGE) += lapic.c
ramstage-y += lapic_cpu_init.c
ramstage-$(CONFIG_SMP) += secondary.S
romstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c
diff --git a/src/cpu/x86/mtrr/Makefile.inc b/src/cpu/x86/mtrr/Makefile.inc
index caa6e9c..47ba4c2 100644
--- a/src/cpu/x86/mtrr/Makefile.inc
+++ b/src/cpu/x86/mtrr/Makefile.inc
@@ -1,4 +1,5 @@
ramstage-y += mtrr.c
+postcar-$(CONFIG_SKIP_RAMSTAGE) += mtrr.c
romstage-y += earlymtrr.c
bootblock-y += earlymtrr.c
diff --git a/src/cpu/x86/name/Makefile.inc b/src/cpu/x86/name/Makefile.inc
index 5dba1a2..e1515496 100644
--- a/src/cpu/x86/name/Makefile.inc
+++ b/src/cpu/x86/name/Makefile.inc
@@ -14,3 +14,4 @@
##
ramstage-y += name.c
+postcar-$(CONFIG_SKIP_RAMSTAGE) += name.c
diff --git a/src/cpu/x86/smm/Makefile.inc b/src/cpu/x86/smm/Makefile.inc
index 32f5ea7..7bcd10e 100644
--- a/src/cpu/x86/smm/Makefile.inc
+++ b/src/cpu/x86/smm/Makefile.inc
@@ -14,10 +14,16 @@
##
ramstage-y += smm_module_loader.c
+postcar-$(CONFIG_SKIP_RAMSTAGE) += smm_module_loader.c
ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y)
$(eval $(call create_class_compiler,smm,x86_32))
$(eval $(call create_class_compiler,smmstub,x86_32))
+#if CONFIG(SKIP_RAMSTAGE)
+else ifeq ($(CONFIG_ARCH_POSTCAR_X86_32),y)
+$(eval $(call create_class_compiler,smm,x86_32))
+$(eval $(call create_class_compiler,smmstub,x86_32))
+#endif
else
$(eval $(call create_class_compiler,smm,x86_64))
$(eval $(call create_class_compiler,smmstub,x86_64))
@@ -36,6 +42,12 @@
@printf " OBJCOPY $(subst $(obj)/,,$(@))\n"
cd $(dir $<); $(OBJCOPY_smm) -I binary $(notdir $<) $(target-objcopy) $(abspath $@)
+ifeq ($(CONFIG_SKIP_RAMSTAGE),y)
+$(call src-to-obj,postcar,$(obj)/cpu/x86/smm/smm.manual): $(obj)/smm/smm
+ @printf " OBJCOPY $(subst $(obj)/,,$(@))\n"
+ cd $(dir $<); $(OBJCOPY_smm) -I binary $(notdir $<) $(target-objcopy) $(abspath $@)
+endif
+
ifeq ($(CONFIG_SMM_TSEG),y)
smmstub-y += smm_stub.S
@@ -45,6 +57,11 @@
ramstage-srcs += $(obj)/cpu/x86/smm/smm.manual
ramstage-srcs += $(obj)/cpu/x86/smm/smmstub.manual
+ifeq ($(CONFIG_SKIP_RAMSTAGE),y)
+postcar-srcs += $(obj)/cpu/x86/smm/smm.manual
+postcar-srcs += $(obj)/cpu/x86/smm/smmstub.manual
+endif
+
# SMM Stub Module. The stub is used as a trampoline for relocation and normal
# SMM handling.
$(obj)/smmstub/smmstub.o: $$(smmstub-objs)
@@ -53,6 +70,10 @@
# Link the SMM stub module with a 0-byte heap.
ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y)
$(eval $(call rmodule_link,$(obj)/smmstub/smmstub.elf, $(obj)/smmstub/smmstub.o, 0,x86_32))
+#if CONFIG(SKIP_RAMSTAGE)
+else ifeq ($(CONFIG_ARCH_POSTCAR_X86_32),y)
+$(eval $(call rmodule_link,$(obj)/smmstub/smmstub.elf, $(obj)/smmstub/smmstub.o, 0,x86_32))
+#endif
else
$(eval $(call rmodule_link,$(obj)/smmstub/smmstub.elf, $(obj)/smmstub/smmstub.o, 0,x86_64))
endif
@@ -64,10 +85,20 @@
@printf " OBJCOPY $(subst $(obj)/,,$(@))\n"
cd $(dir $<); $(OBJCOPY_smmstub) -I binary $(notdir $<) $(target-objcopy) $(abspath $@)
+ifeq ($(CONFIG_SKIP_RAMSTAGE),y)
+$(call src-to-obj,postcar,$(obj)/cpu/x86/smm/smmstub.manual): $(obj)/smmstub/smmstub
+ @printf " OBJCOPY $(subst $(obj)/,,$(@))\n"
+ cd $(dir $<); $(OBJCOPY_smmstub) -I binary $(notdir $<) $(target-objcopy) $(abspath $@)
+endif
+
# C-based SMM handler.
ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y)
$(eval $(call rmodule_link,$(obj)/smm/smm.elf, $(obj)/smm/smm.o, $(CONFIG_SMM_MODULE_HEAP_SIZE),x86_32))
+#if CONFIG(SKIP_RAMSTAGE)
+else ifeq ($(CONFIG_ARCH_POSTCAR_X86_32),y)
+$(eval $(call rmodule_link,$(obj)/smm/smm.elf, $(obj)/smm/smm.o, $(CONFIG_SMM_MODULE_HEAP_SIZE),x86_32))
+#endif
else
$(eval $(call rmodule_link,$(obj)/smm/smm.elf, $(obj)/smm/smm.o, $(CONFIG_SMM_MODULE_HEAP_SIZE),x86_64))
endif
@@ -84,6 +115,9 @@
ifeq ($(CONFIG_HAVE_SMI_HANDLER),y)
ramstage-srcs += $(obj)/cpu/x86/smm/smm.manual
+ifeq ($(CONFIG_SKIP_RAMSTAGE),y)
+postcar-srcs += $(obj)/cpu/x86/smm/smm.manual
+endif
endif
smm-y += smmhandler.S
diff --git a/src/device/Makefile.inc b/src/device/Makefile.inc
index baa45be..90c814d 100644
--- a/src/device/Makefile.inc
+++ b/src/device/Makefile.inc
@@ -7,6 +7,13 @@
ramstage-$(CONFIG_ARCH_RAMSTAGE_X86_64) += pnp_device.c
ramstage-y += smbus_ops.c
+ifeq ($(CONFIG_SKIP_RAMSTAGE),y)
+postcar-y += device.c
+postcar-y += root_device.c
+postcar-y += cpu_device.c
+postcar-y += device_util.c
+endif
+
ifeq ($(CONFIG_AZALIA_PLUGIN_SUPPORT),y)
ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c
endif
@@ -22,7 +29,16 @@
bootblock-y += pci_early.c
verstage-y += pci_early.c
romstage-y += pci_early.c
+
+ifneq ($(CONFIG_SKIP_RAMSTAGE),y)
postcar-y += pci_early.c
+else
+postcar-y += pci_device.c
+postcar-y += pci_rom.c
+postcar-$(CONFIG_PCIX_PLUGIN_SUPPORT) += pcix_device.c
+postcar-$(CONFIG_PCIEXP_PLUGIN_SUPPORT) += pciexp_device.c
+postcar-$(CONFIG_CARDBUS_PLUGIN_SUPPORT) += cardbus_device.c
+endif
ramstage-y += pci_class.c
ramstage-y += pci_device.c
diff --git a/src/drivers/elog/Makefile.inc b/src/drivers/elog/Makefile.inc
index cce1c3d..fcf995f 100644
--- a/src/drivers/elog/Makefile.inc
+++ b/src/drivers/elog/Makefile.inc
@@ -1,7 +1,11 @@
bootblock-$(CONFIG_ELOG_PRERAM) += elog.c
verstage-$(CONFIG_ELOG_PRERAM) += elog.c
romstage-$(CONFIG_ELOG_PRERAM) += elog.c
+ifneq ($(CONFIG_SKIP_RAMSTAGE),y)
postcar-$(CONFIG_ELOG_PRERAM) += elog.c
+else
+postcar-$(CONFIG_ELOG) += elog.c
+endif
ramstage-$(CONFIG_ELOG) += elog.c
smm-$(CONFIG_ELOG_GSMI) += elog.c gsmi.c
diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc
index d627a3d..b363214 100644
--- a/src/drivers/intel/fsp2_0/Makefile.inc
+++ b/src/drivers/intel/fsp2_0/Makefile.inc
@@ -39,6 +39,13 @@
ramstage-y += util.c
ramstage-$(CONFIG_MMA) += mma_core.c
+ifeq ($(CONFIG_SKIP_RAMSTAGE),y)
+postcar-$(CONFIG_RUN_FSP_GOP) += graphics.c
+postcar-y += silicon_init.c
+postcar-y += util.c
+postcar-y += debug.c
+endif
+
postcar-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c
postcar-$(CONFIG_FSP_CAR) += temp_ram_exit.c
postcar-$(CONFIG_FSP_CAR) += util.c
diff --git a/src/drivers/intel/fsp2_0/ppi/Makefile.inc b/src/drivers/intel/fsp2_0/ppi/Makefile.inc
index 67c4966..dc75f29 100644
--- a/src/drivers/intel/fsp2_0/ppi/Makefile.inc
+++ b/src/drivers/intel/fsp2_0/ppi/Makefile.inc
@@ -13,4 +13,7 @@
# GNU General Public License for more details.
#
+ifeq ($(CONFIG_SKIP_RAMSTAGE),y)
+postcar-$(CONFIG_FSP_USES_MP_SERVICES_PPI) += mp_service_ppi.c
+endif
ramstage-$(CONFIG_FSP_USES_MP_SERVICES_PPI) += mp_service_ppi.c
diff --git a/src/drivers/intel/gma/Makefile.inc b/src/drivers/intel/gma/Makefile.inc
index e128ad6..3a6af8b 100644
--- a/src/drivers/intel/gma/Makefile.inc
+++ b/src/drivers/intel/gma/Makefile.inc
@@ -20,7 +20,9 @@
endif
ramstage-$(CONFIG_INTEL_GMA_ACPI) += acpi.c
ramstage-$(CONFIG_INTEL_GMA_ACPI) += opregion.c
-
+ifeq ($(CONFIG_SKIP_RAMSTAGE),y)
+postcar-$(CONFIG_INTEL_GMA_ACPI) += opregion.c
+endif
# add_vbt_to_cbfs, first argument is the filename in cbfs, the second one
# is the filename in the coreboot tree.
add_vbt_to_cbfs= \
diff --git a/src/drivers/mrc_cache/Makefile.inc b/src/drivers/mrc_cache/Makefile.inc
index 0d226fe..a58285f 100644
--- a/src/drivers/mrc_cache/Makefile.inc
+++ b/src/drivers/mrc_cache/Makefile.inc
@@ -1,2 +1,5 @@
romstage-$(CONFIG_CACHE_MRC_SETTINGS) += mrc_cache.c
+ifeq ($(CONFIG_SKIP_RAMSTAGE),y)
+postcar-$(CONFIG_CACHE_MRC_SETTINGS) += mrc_cache.c
+endif
ramstage-$(CONFIG_CACHE_MRC_SETTINGS) += mrc_cache.c
diff --git a/src/drivers/pc80/pc/Makefile.inc b/src/drivers/pc80/pc/Makefile.inc
index 8c348e3..86dcd94 100644
--- a/src/drivers/pc80/pc/Makefile.inc
+++ b/src/drivers/pc80/pc/Makefile.inc
@@ -1,5 +1,6 @@
ifeq ($(CONFIG_ARCH_X86),y)
+postcar-$(CONFIG_SKIP_RAMSTAGE) += isa-dma.c
ramstage-y += isa-dma.c
ramstage-y += i8254.c
ramstage-y += i8259.c
diff --git a/src/ec/google/chromeec/Makefile.inc b/src/ec/google/chromeec/Makefile.inc
index 4593c73..44b5eb8 100644
--- a/src/ec/google/chromeec/Makefile.inc
+++ b/src/ec/google/chromeec/Makefile.inc
@@ -34,6 +34,12 @@
romstage-$(CONFIG_EC_GOOGLE_CHROMEEC_SWITCHES) += switches.c
ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC_SWITCHES) += switches.c
+ifeq ($(CONFIG_SKIP_RAMSTAGE),y)
+postcar-y += ec.c
+postcar-$(CONFIG_EC_GOOGLE_CHROMEEC_LPC) += ec_lpc.c
+postcar-$(CONFIG_EC_GOOGLE_CHROMEEC_SWITCHES) += switches.c
+endif
+
CHROMEEC_SOURCE ?= $(top)/3rdparty/chromeec
# These are Chrome EC firmware images that a payload (such as depthcharge) can
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index 1350152..6a1b5c1 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -165,6 +165,18 @@
postcar-y += imd_cbmem.c
postcar-y += imd.c
postcar-y += romstage_handoff.c
+ifeq ($(CONFIG_SKIP_RAMSTAGE),y)
+postcar-y += region_file.c
+postcar-y += selfboot.c
+postcar-y += coreboot_table.c
+postcar-y += bootmem.c
+postcar-y += malloc.c
+postcar-y += fallback_boot.c
+postcar-y += compute_ip_checksum.c
+postcar-y += stack.c
+postcar-y += wrdd.c
+postcar-y += memrange.c
+endif
bootblock-y += hexdump.c
ramstage-y += hexdump.c
diff --git a/src/security/vboot/Makefile.inc b/src/security/vboot/Makefile.inc
index 6d2096d..f4217ba 100644
--- a/src/security/vboot/Makefile.inc
+++ b/src/security/vboot/Makefile.inc
@@ -47,6 +47,13 @@
romstage-$(CONFIG_VBOOT_VBNV_CMOS_BACKUP_TO_FLASH) += vbnv_flash.c
ramstage-$(CONFIG_VBOOT_VBNV_CMOS_BACKUP_TO_FLASH) += vbnv_flash.c
+ifeq ($(CONFIG_SKIP_RAMSTAGE),y)
+postcar-y += gbb.c
+postcar-y += vbnv.c
+postcar-$(CONFIG_VBOOT_VBNV_CMOS) += vbnv_cmos.c
+postcar-$(CONFIG_VBOOT_VBNV_CMOS_BACKUP_TO_FLASH) += vbnv_flash.c
+endif
+
bootblock-$(CONFIG_VBOOT_VBNV_EC) += vbnv_ec.c
verstage-$(CONFIG_VBOOT_VBNV_EC) += vbnv_ec.c
romstage-$(CONFIG_VBOOT_VBNV_EC) += vbnv_ec.c
diff --git a/src/soc/intel/common/Makefile.inc b/src/soc/intel/common/Makefile.inc
index 22d350c..9d131a3 100644
--- a/src/soc/intel/common/Makefile.inc
+++ b/src/soc/intel/common/Makefile.inc
@@ -21,6 +21,11 @@
ramstage-y += vbt.c
ramstage-$(CONFIG_SOC_INTEL_COMMON_NHLT) += nhlt.c
+ifeq ($(CONFIG_SKIP_RAMSTAGE),y)
+postcar-$(CONFIG_SOC_INTEL_COMMON_ACPI_WAKE_SOURCE) += acpi_wake_source.c
+postcar-y += vbt.c
+endif
+
bootblock-$(CONFIG_TPM_CR50) += tpm_tis.c
verstage-$(CONFIG_TPM_CR50) += tpm_tis.c
romstage-$(CONFIG_TPM_CR50) += tpm_tis.c
diff --git a/src/vendorcode/google/chromeos/Makefile.inc b/src/vendorcode/google/chromeos/Makefile.inc
index 000d056..5b72336 100644
--- a/src/vendorcode/google/chromeos/Makefile.inc
+++ b/src/vendorcode/google/chromeos/Makefile.inc
@@ -13,6 +13,12 @@
## GNU General Public License for more details.
##
+ifeq ($(CONFIG_SKIP_RAMSTAGE),y)
+postcar-$(CONFIG_HAVE_ACPI_TABLES) += gnvs.c
+postcar-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c
+postcar-$(CONFIG_CHROMEOS_RAMOOPS) += ramoops.c
+endif
+
ramstage-$(CONFIG_ELOG) += elog.c
ramstage-$(CONFIG_HAVE_ACPI_TABLES) += gnvs.c
ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c
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