Alper Nebi Yasak has uploaded this change for review.

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mainboard/qemu-riscv: Add PCI support

Add PCI support for the qemu-riscv mainboard like how it is done for
qemu-aarch64. The resulting build can be used with a QEMU command line
like:

    util/riscv/make-spike-elf.sh build/coreboot.{rom,elf}
    qemu-system-riscv64 \
        -display gtk,show-tabs=on \
        -bios build/coreboot.elf \
        -M virt -m 1G \
        -device pcie-root-port \
        -serial stdio -device VGA \
        ...

Change-Id: Ie57b35620af82c681d1f0d78fa8e514e4df0d2ac
Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
---
A src/arch/riscv/include/arch/pci_ops.h
M src/mainboard/emulation/qemu-riscv/Kconfig
M src/mainboard/emulation/qemu-riscv/devicetree.cb
M src/mainboard/emulation/qemu-riscv/include/mainboard/addressmap.h
M src/mainboard/emulation/qemu-riscv/mainboard.c
5 files changed, 60 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/80378/1

diff --git a/src/arch/riscv/include/arch/pci_ops.h b/src/arch/riscv/include/arch/pci_ops.h
new file mode 100644
index 0000000..d127a24
--- /dev/null
+++ b/src/arch/riscv/include/arch/pci_ops.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef ARCH_RISCV_PCI_OPS_H
+#define ARCH_RISCV_PCI_OPS_H
+
+#include <device/pci_mmio_cfg.h>
+
+#endif
diff --git a/src/mainboard/emulation/qemu-riscv/Kconfig b/src/mainboard/emulation/qemu-riscv/Kconfig
index 091c432..a966967f 100644
--- a/src/mainboard/emulation/qemu-riscv/Kconfig
+++ b/src/mainboard/emulation/qemu-riscv/Kconfig
@@ -29,6 +29,13 @@
 	select MISSING_BOARD_RESET
 	select DRIVERS_UART_8250MEM
 	select RISCV_HAS_OPENSBI
+	select PCI
+
+config ECAM_MMCONF_BASE_ADDRESS
+	default 0x30000000
+
+config ECAM_MMCONF_BUS_NUMBER
+	default 256
 
 config MEMLAYOUT_LD_FILE
 	string
diff --git a/src/mainboard/emulation/qemu-riscv/devicetree.cb b/src/mainboard/emulation/qemu-riscv/devicetree.cb
index 120af99..bb3fd6b 100644
--- a/src/mainboard/emulation/qemu-riscv/devicetree.cb
+++ b/src/mainboard/emulation/qemu-riscv/devicetree.cb
@@ -2,4 +2,8 @@
 
 chip soc/ucb/riscv
 	device cpu_cluster 0 on end
+
+	device domain 0 on ops qemu_riscv_pci_domain_ops
+		device pci 00.0 on end
+	end
 end
diff --git a/src/mainboard/emulation/qemu-riscv/include/mainboard/addressmap.h b/src/mainboard/emulation/qemu-riscv/include/mainboard/addressmap.h
index 27baeb7..da21d66 100644
--- a/src/mainboard/emulation/qemu-riscv/include/mainboard/addressmap.h
+++ b/src/mainboard/emulation/qemu-riscv/include/mainboard/addressmap.h
@@ -5,3 +5,12 @@
 #define QEMU_VIRT_UART0		0x10000000
 #define QEMU_VIRT_VIRTIO	0x10001000
 #define QEMU_VIRT_DRAM		0x80000000
+
+#define QEMU_VIRT_PCIE_LOW_MMIO_BASE 0x40000000
+#define QEMU_VIRT_PCIE_LOW_MMIO_LIMIT 0x80000000
+
+#define QEMU_VIRT_PCIE_ECAM_BASE 0x30000000
+#define QEMU_VIRT_PCIE_ECAM_SIZE 0x3fffffff
+
+#define QEMU_VIRT_PCIE_HIGH_MMIO_BASE 0x300000000ULL
+#define QEMU_VIRT_PCIE_HIGH_MMIO_LIMIT 0x3ffffffffULL
diff --git a/src/mainboard/emulation/qemu-riscv/mainboard.c b/src/mainboard/emulation/qemu-riscv/mainboard.c
index f0f0740..2e07781 100644
--- a/src/mainboard/emulation/qemu-riscv/mainboard.c
+++ b/src/mainboard/emulation/qemu-riscv/mainboard.c
@@ -4,6 +4,7 @@
 #include <device/device.h>
 #include <symbols.h>
 #include <ramdetect.h>
+#include <mainboard/addressmap.h>
 
 static void mainboard_enable(struct device *dev)
 {
@@ -20,3 +21,34 @@
 struct chip_operations mainboard_ops = {
 	.enable_dev = mainboard_enable,
 };
+
+struct chip_operations mainboard_emulation_qemu_riscv_ops = { };
+
+static void qemu_riscv_domain_read_resources(struct device *dev)
+{
+	struct resource *res;
+	int index = 0;
+	/* Initialize the system-wide I/O space constraints. */
+	res = new_resource(dev, index++);
+	res->limit = 0xffff;
+	res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED;
+
+	/* Initialize the system-wide memory resources constraints. */
+	res = new_resource(dev, index++);
+	res->base = QEMU_VIRT_PCIE_LOW_MMIO_BASE;
+	res->limit = QEMU_VIRT_PCIE_LOW_MMIO_LIMIT;
+	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED;
+
+	res = new_resource(dev, index++);
+	res->base = QEMU_VIRT_PCIE_HIGH_MMIO_BASE;
+	res->limit = QEMU_VIRT_PCIE_HIGH_MMIO_LIMIT;
+	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED;
+
+	mmio_range(dev, index++, QEMU_VIRT_PCIE_ECAM_BASE, QEMU_VIRT_PCIE_ECAM_SIZE);
+}
+
+struct device_operations qemu_riscv_pci_domain_ops = {
+	.read_resources    = qemu_riscv_domain_read_resources,
+	.set_resources     = pci_domain_set_resources,
+	.scan_bus          = pci_host_bridge_scan_bus,
+};

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