Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/26706
Change subject: cpu/intel/car/cache_as_ram_ht.inc: Allow setting non eviction mode ......................................................................
cpu/intel/car/cache_as_ram_ht.inc: Allow setting non eviction mode
This is needed on CPU's from model_2065x on.
Change-Id: Iefd484a95fff8d1cb78b4dcf5b31df7086e4431f Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/cpu/intel/car/cache_as_ram_ht.inc 1 file changed, 34 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/26706/1
diff --git a/src/cpu/intel/car/cache_as_ram_ht.inc b/src/cpu/intel/car/cache_as_ram_ht.inc index 0eb58d1..58dbf29 100644 --- a/src/cpu/intel/car/cache_as_ram_ht.inc +++ b/src/cpu/intel/car/cache_as_ram_ht.inc @@ -28,6 +28,8 @@ #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
+#define NoEvictMod_MSR 0x2e0 + /* Save the BIST result. */ movl %eax, %ebp
@@ -299,6 +301,15 @@ invd movl %eax, %cr0
+#if IS_ENABLED(CONFIG_CPU_HAS_NO_EVICT_MODE) + /* enable the 'no eviction' mode */ + movl $NoEvictMod_MSR, %ecx + rdmsr + orl $1, %eax + andl $~2, %eax + wrmsr +#endif + /* Clear the cache memory region. This will also fill up the cache. */ cld xorl %eax, %eax @@ -306,6 +317,14 @@ movl $(CACHE_AS_RAM_SIZE >> 2), %ecx rep stosl
+#if IS_ENABLED(CONFIG_CPU_HAS_NO_EVICT_MODE) + /* enable the 'no eviction run' state */ + movl $NoEvictMod_MSR, %ecx + rdmsr + orl $3, %eax + wrmsr +#endif + post_code(0x2d) /* Enable Cache-as-RAM mode by disabling cache. */ movl %cr0, %eax @@ -370,8 +389,23 @@
post_code(0x32)
+#if IS_ENABLED(CONFIG_CPU_HAS_NO_EVICT_MODE) + /* Disable the no eviction run state */ + movl $NoEvictMod_MSR, %ecx + rdmsr + andl $~2, %eax + wrmsr +#endif + invd
+#if IS_ENABLED(CONFIG_CPU_HAS_NO_EVICT_MODE) + /* Disable the no eviction mode */ + rdmsr + andl $~1, %eax + wrmsr +#endif + post_code(0x33)
/* Enable cache. */