Nico Huber has uploaded this change for review.

View Change

[UNTESTED] nb/intel/ironlake: Reserve gap betwen TSEG and BGSM

There may be a gap between TSEG and the graphics stolen memory due to
the alignment done in `raminit.c`. If we allocate MMIO resources in
this range, it misbehaves unpredictably, so reserve it.

Change-Id: If305e9751ebf4edc945cf038ed72698f3696e52d
Signed-off-by: Nico Huber <nico.h@gmx.de>
---
M src/northbridge/intel/ironlake/northbridge.c
1 file changed, 7 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/45325/1

diff --git a/src/northbridge/intel/ironlake/northbridge.c b/src/northbridge/intel/ironlake/northbridge.c
index 9b7ea85..cf014fe 100644
--- a/src/northbridge/intel/ironlake/northbridge.c
+++ b/src/northbridge/intel/ironlake/northbridge.c
@@ -92,7 +92,7 @@
 
 static void mc_read_resources(struct device *dev)
 {
-	uint32_t tseg_base;
+	uint32_t tseg_base, tseg_end;
 	uint64_t touud;
 	uint16_t reg16;
 	int index = 3;
@@ -102,6 +102,7 @@
 	mmconf_resource(dev, 0x50);
 
 	tseg_base = pci_read_config32(pcidev_on_root(0, 0), TSEG);
+	tseg_end = tseg_base + CONFIG_SMM_TSEG_SIZE;
 	touud = pci_read_config16(pcidev_on_root(0, 0),
 				  TOUUD);
 
@@ -131,6 +132,11 @@
 	    pci_read_config32(pcidev_on_root(0, 0), IGD_BASE);
 	gtt_base =
 	    pci_read_config32(pcidev_on_root(0, 0), GTT_BASE);
+	if (gtt_base > tseg_end) {
+		/* Reserve the gap. MMIO doesn't work in this range. Keep
+		   it uncacheable, though, for easier MTRR allocation. */
+		mmio_resource(dev, index++, tseg_end >> 10, (gtt_base - tseg_end) >> 10);
+	}
 	mmio_resource(dev, index++, gtt_base >> 10, uma_size_gtt << 10);
 	mmio_resource(dev, index++, igd_base >> 10, uma_size_igd << 10);
 

To view, visit change 45325. To unsubscribe, or for help writing mail filters, visit settings.