Subrata Banik submitted this change.
5 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
soc/intel/cmn/sa: Refactor SA common code
Leverages common SA header definitions for Host Bridge registers.
Renames DSM_BASE_ADDR_REG to BDSM and DPR_REG to DPR for brevity.
Additionally, made some minor code alignment corrections while
adding newer macros in the header file.
TEST= Build and boot successful on google/screebo.
Change-Id: I476f213d75a0978336b3749a5ba1499107eb2238
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80361
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: sridhar siricilla <siricillasridhar@gmail.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
---
M src/soc/intel/alderlake/include/soc/systemagent.h
M src/soc/intel/alderlake/systemagent.c
M src/soc/intel/common/block/include/intelblocks/systemagent.h
M src/soc/intel/common/block/systemagent/systemagent_def.h
M src/soc/intel/meteorlake/include/soc/systemagent.h
M src/soc/intel/meteorlake/systemagent.c
6 files changed, 32 insertions(+), 41 deletions(-)
diff --git a/src/soc/intel/alderlake/include/soc/systemagent.h b/src/soc/intel/alderlake/include/soc/systemagent.h
index 36d3398..b7a2957 100644
--- a/src/soc/intel/alderlake/include/soc/systemagent.h
+++ b/src/soc/intel/alderlake/include/soc/systemagent.h
@@ -64,17 +64,14 @@
#define LT_SECURITY_SIZE (128 * KiB)
#define APIC_SIZE (1 * MiB)
-#define MASK_PCIEXBAR_LENGTH 0x0000000E // bits [3:1]
-#define PCIEXBAR_LENGTH_LSB 1 // used to shift right
-
-#define DSM_BASE_ADDR_REG 0xB0
-#define MASK_DSM_LENGTH 0xFF00 // [15:8]
-#define MASK_DSM_LENGTH_LSB 8 // used to shift right
-#define MASK_GSM_LENGTH 0xC0 // [7:6]
-#define MASK_GSM_LENGTH_LSB 6 // used to shift right
-#define DPR_REG 0x5C
-#define MASK_DPR_LENGTH 0xFF0 // [11:4]
-#define MASK_DPR_LENGTH_LSB 4 // used to shift right
+#define MASK_PCIEXBAR_LENGTH 0xE /* bits [3:1] */
+#define PCIEXBAR_LENGTH_LSB 1 /* used to shift right */
+#define MASK_DSM_LENGTH 0xFF00 /* bits [15:8] */
+#define MASK_DSM_LENGTH_LSB 8 /* used to shift right */
+#define MASK_GSM_LENGTH 0xC0 /* bits [7:6] */
+#define MASK_GSM_LENGTH_LSB 6 /* used to shift right */
+#define MASK_DPR_LENGTH 0xFF0 /* bits [11:4] */
+#define MASK_DPR_LENGTH_LSB 4 /* used to shift right */
uint64_t get_mmcfg_size(const struct device *dev);
uint64_t get_dsm_size(const struct device *dev);
diff --git a/src/soc/intel/alderlake/systemagent.c b/src/soc/intel/alderlake/systemagent.c
index 36fa45b..ecd704e 100644
--- a/src/soc/intel/alderlake/systemagent.c
+++ b/src/soc/intel/alderlake/systemagent.c
@@ -111,7 +111,7 @@
/* DSM */
size = get_dsm_size(dev);
if (size > 0) {
- base = pci_read_config32(dev, DSM_BASE_ADDR_REG) & 0xFFF00000;
+ base = pci_read_config32(dev, BDSM) & 0xFFF00000;
set_mmio_resource(&(cfg_rsrc[count++]), base, size, "DSM");
}
@@ -316,7 +316,7 @@
uint64_t get_dpr_size(const struct device *dev)
{
uint64_t size;
- uint32_t dpr_reg = pci_read_config32(dev, DPR_REG);
+ uint32_t dpr_reg = pci_read_config32(dev, DPR);
uint32_t size_field = (dpr_reg & MASK_DPR_LENGTH) >> MASK_DPR_LENGTH_LSB;
size = (uint64_t)size_field * MiB;
return size;
diff --git a/src/soc/intel/common/block/include/intelblocks/systemagent.h b/src/soc/intel/common/block/include/intelblocks/systemagent.h
index 64e9be6..3d4ff25 100644
--- a/src/soc/intel/common/block/include/intelblocks/systemagent.h
+++ b/src/soc/intel/common/block/include/intelblocks/systemagent.h
@@ -10,12 +10,18 @@
/* Device 0:0.0 PCI configuration space */
#define MCHBAR 0x48
-#define PCIEXBAR 0x60
-#define TOUUD 0xa8 /* Top of Upper Usable DRAM */
-#define BDSM 0xb0 /* Base Data Stolen Memory */
-#define BGSM 0xb4 /* Base GTT Stolen Memory */
-#define TSEG 0xb8 /* TSEG base */
-#define TOLUD 0xbc /* Top of Low Used Memory */
+#define GGC 0x50 /* GMCH Graphics Control Register */
+#define G_GMS_OFFSET 0x8
+#define G_GMS_MASK 0xff00
+#define G_GGMS_OFFSET 0x6
+#define G_GGMS_MASK 0xc0
+#define DPR 0x5C /* DMA Protected Range Register */
+#define PCIEXBAR 0x60
+#define TOUUD 0xa8 /* Top of Upper Usable DRAM */
+#define BDSM 0xb0 /* Base Data Stolen Memory */
+#define BGSM 0xb4 /* Base GTT Stolen Memory */
+#define TSEG 0xb8 /* TSEG base */
+#define TOLUD 0xbc /* Top of Low Used Memory */
/* PCIEXBAR register fields */
#define PCIEXBAR_LENGTH_4096MB 6
@@ -27,13 +33,6 @@
#define PCIEXBAR_LENGTH_256MB 0
#define PCIEXBAR_PCIEXBAREN (1 << 0)
-/* GMCH Graphics Control Register */
-#define GGC 0x50
-#define G_GMS_OFFSET 0x8
-#define G_GMS_MASK 0xff00
-#define G_GGMS_OFFSET 0x6
-#define G_GGMS_MASK 0xc0
-
/* MCHBAR */
#define MCHBAR8(x) (*(volatile u8 *)(uintptr_t)(MCH_BASE_ADDRESS + x))
#define MCHBAR16(x) (*(volatile u16 *)(uintptr_t)(MCH_BASE_ADDRESS + x))
diff --git a/src/soc/intel/common/block/systemagent/systemagent_def.h b/src/soc/intel/common/block/systemagent/systemagent_def.h
index 09a99ea..f913843 100644
--- a/src/soc/intel/common/block/systemagent/systemagent_def.h
+++ b/src/soc/intel/common/block/systemagent/systemagent_def.h
@@ -5,9 +5,7 @@
/* Device 0:0.0 PCI configuration space */
-
/* DPR register in case CONFIG_SA_ENABLE_DPR is selected by SoC */
-#define DPR 0x5c
#define DPR_EPM (1 << 2)
#define DPR_PRS (1 << 1)
#define DPR_SIZE_MASK 0xff0
diff --git a/src/soc/intel/meteorlake/include/soc/systemagent.h b/src/soc/intel/meteorlake/include/soc/systemagent.h
index d463ce1..05356ff 100644
--- a/src/soc/intel/meteorlake/include/soc/systemagent.h
+++ b/src/soc/intel/meteorlake/include/soc/systemagent.h
@@ -50,17 +50,14 @@
#define LT_SECURITY_SIZE (384 * KiB)
#define APIC_SIZE (1 * MiB)
-#define MASK_PCIEXBAR_LENGTH 0x0000000E // bits [3:1]
-#define PCIEXBAR_LENGTH_LSB 1 // used to shift right
-
-#define DSM_BASE_ADDR_REG 0xB0
-#define MASK_DSM_LENGTH 0xFF00 // [15:8]
-#define MASK_DSM_LENGTH_LSB 8 // used to shift right
-#define MASK_GSM_LENGTH 0xC0 // [7:6]
-#define MASK_GSM_LENGTH_LSB 6 // used to shift right
-#define DPR_REG 0x5C
-#define MASK_DPR_LENGTH 0xFF0 // [11:4]
-#define MASK_DPR_LENGTH_LSB 4 // used to shift right
+#define MASK_PCIEXBAR_LENGTH 0x0000000E /* bits [3:1] */
+#define PCIEXBAR_LENGTH_LSB 1 /* used to shift right */
+#define MASK_DSM_LENGTH 0xFF00 /* bits [15:8] */
+#define MASK_DSM_LENGTH_LSB 8 /* used to shift right */
+#define MASK_GSM_LENGTH 0xC0 /* bits [7:6] */
+#define MASK_GSM_LENGTH_LSB 6 /* used to shift right */
+#define MASK_DPR_LENGTH 0xFF0 /* bits [11:4] */
+#define MASK_DPR_LENGTH_LSB 4 /* used to shift right */
uint64_t get_mmcfg_size(const struct device *dev);
uint64_t get_dsm_size(const struct device *dev);
diff --git a/src/soc/intel/meteorlake/systemagent.c b/src/soc/intel/meteorlake/systemagent.c
index 875ddcc..a6c8c71 100644
--- a/src/soc/intel/meteorlake/systemagent.c
+++ b/src/soc/intel/meteorlake/systemagent.c
@@ -103,7 +103,7 @@
/* DSM */
size = get_dsm_size(dev);
if (size > 0) {
- base = pci_read_config32(dev, DSM_BASE_ADDR_REG) & 0xFFF00000;
+ base = pci_read_config32(dev, BDSM) & 0xFFF00000;
set_mmio_resource(&(cfg_rsrc[count++]), base, size, "DSM");
}
@@ -325,7 +325,7 @@
uint64_t get_dpr_size(const struct device *dev)
{
uint64_t size;
- uint32_t dpr_reg = pci_read_config32(dev, DPR_REG);
+ uint32_t dpr_reg = pci_read_config32(dev, DPR);
uint32_t size_field = (dpr_reg & MASK_DPR_LENGTH) >> MASK_DPR_LENGTH_LSB;
size = (uint64_t)size_field * MiB;
return size;
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