Subrata Banik submitted this change.
soc/intel/apollolake: Make SMI_STS offset macro definition consistent
This patch makes all bit field macro definition for SMI_STS register
(offset 0x44) be consistent i.e. ending with "_STS_BIT".
Also modified relevant files where those macros are getting used.
Change-Id: Ibe3fbb459c106a3a58cd9a8b6eb3d7ee92e6ed82
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39022
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
---
M src/soc/intel/apollolake/include/soc/pm.h
M src/soc/intel/apollolake/pmutil.c
M src/soc/intel/apollolake/smihandler.c
3 files changed, 52 insertions(+), 51 deletions(-)
diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h
index 22e414c..0cf06b2 100644
--- a/src/soc/intel/apollolake/include/soc/pm.h
+++ b/src/soc/intel/apollolake/include/soc/pm.h
@@ -105,29 +105,30 @@
(ESPI_SMI_EN | APMC_EN | SLP_SMI_EN | GBL_SMI_EN | EOS | GPIO_EN)
#define SMI_STS 0x44
+#define SMI_STS_BITS 32
/* Bits for SMI status */
#define ESPI_SMI_STS_BIT 28
-#define PMC_OCP_SMI_STS 27
-#define SPI_SMI_STS 26
-#define SPI_SSMI_STS 25
-#define SCC2_SMI_STS 21
-#define PCIE_SMI_STS 20
-#define SCS_SMI_STS 19
-#define HSMBUS_SMI_STS 18
-#define XHCI_SMI_STS 17
-#define SMBUS_SMI_STS 16
-#define SERIRQ_SMI_STS 15
-#define PERIODIC_SMI_STS 14
-#define TCO_SMI_STS 13
-#define MC_SMI_STS 12
-#define GPIO_UNLOCK_SMI_STS 11
-#define GPIO_SMI_STS 10
-#define FAKE_PM1_SMI_STS 8
-#define SWSMI_TMR_SMI_STS 6
-#define APM_SMI_STS 5
-#define SLP_SMI_STS 4
-#define LEGACY_USB_SMI_STS 3
-#define BIOS_SMI_STS 2
+#define PMC_OCP_SMI_STS_BIT 27
+#define SPI_SMI_STS_BIT 26
+#define SPI_SSMI_STS_BIT 25
+#define SCC2_SMI_STS_BIT 21
+#define PCI_EXP_SMI_STS_BIT 20
+#define SCS_SMI_STS_BIT 19
+#define HSMBUS_SMI_STS_BIT 18
+#define XHCI_SMI_STS_BIT 17
+#define SMBUS_SMI_STS_BIT 16
+#define SERIRQ_SMI_STS_BIT 15
+#define PERIODIC_STS_BIT 14
+#define TCO_STS_BIT 13
+#define MC_SMI_STS_BIT 12
+#define GPIO_UNLOCK_SMI_STS_BIT 11
+#define GPIO_STS_BIT 10
+#define PM1_STS_BIT 8
+#define SWSMI_TMR_STS_BIT 6
+#define APM_STS_BIT 5
+#define SMI_ON_SLP_EN_STS_BIT 4
+#define LEGACY_USB_STS_BIT 3
+#define BIOS_STS_BIT 2
#define GPE_CNTL 0x50
#define DEVACT_STS 0x4c
diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c
index 8151afc..4a08827 100644
--- a/src/soc/intel/apollolake/pmutil.c
+++ b/src/soc/intel/apollolake/pmutil.c
@@ -57,27 +57,27 @@
const char *const *soc_smi_sts_array(size_t *a)
{
static const char *const smi_sts_bits[] = {
- [BIOS_SMI_STS] = "BIOS",
- [LEGACY_USB_SMI_STS] = "LEGACY USB",
- [SLP_SMI_STS] = "SLP_SMI",
- [APM_SMI_STS] = "APM",
- [SWSMI_TMR_SMI_STS] = "SWSMI_TMR",
- [FAKE_PM1_SMI_STS] = "PM1",
- [GPIO_SMI_STS] = "GPIO_SMI",
- [GPIO_UNLOCK_SMI_STS] = "GPIO_UNLOCK_SSMI",
- [MC_SMI_STS] = "MCSMI",
- [TCO_SMI_STS] = "TCO",
- [PERIODIC_SMI_STS] = "PERIODIC",
- [SERIRQ_SMI_STS] = "SERIRQ",
- [SMBUS_SMI_STS] = "SMBUS_SMI",
- [XHCI_SMI_STS] = "XHCI",
- [HSMBUS_SMI_STS] = "HOST_SMBUS",
- [SCS_SMI_STS] = "SCS",
- [PCIE_SMI_STS] = "PCI_EXP_SMI",
- [SCC2_SMI_STS] = "SCC2",
- [SPI_SSMI_STS] = "SPI_SSMI",
- [SPI_SMI_STS] = "SPI",
- [PMC_OCP_SMI_STS] = "OCP_CSE",
+ [BIOS_STS_BIT] = "BIOS",
+ [LEGACY_USB_STS_BIT] = "LEGACY USB",
+ [SMI_ON_SLP_EN_STS_BIT] = "SLP_SMI",
+ [APM_STS_BIT] = "APM",
+ [SWSMI_TMR_STS_BIT] = "SWSMI_TMR",
+ [PM1_STS_BIT] = "PM1",
+ [GPIO_STS_BIT] = "GPIO_SMI",
+ [GPIO_UNLOCK_SMI_STS_BIT] = "GPIO_UNLOCK_SSMI",
+ [MC_SMI_STS_BIT] = "MCSMI",
+ [TCO_STS_BIT] = "TCO",
+ [PERIODIC_STS_BIT] = "PERIODIC",
+ [SERIRQ_SMI_STS_BIT] = "SERIRQ",
+ [SMBUS_SMI_STS_BIT] = "SMBUS_SMI",
+ [XHCI_SMI_STS_BIT] = "XHCI",
+ [SCS_SMI_STS_BIT] = "HOST_SMBUS",
+ [SCS_SMI_STS_BIT] = "SCS",
+ [PCI_EXP_SMI_STS_BIT] = "PCI_EXP_SMI",
+ [SCC2_SMI_STS_BIT] = "SCC2",
+ [SPI_SSMI_STS_BIT] = "SPI_SSMI",
+ [SPI_SMI_STS_BIT] = "SPI",
+ [PMC_OCP_SMI_STS_BIT] = "OCP_CSE",
};
*a = ARRAY_SIZE(smi_sts_bits);
@@ -98,7 +98,7 @@
/* Fake PM1 status bit if power button pressed. */
if (pm1_sts & PWRBTN_STS)
- generic_sts |= (1 << FAKE_PM1_SMI_STS);
+ generic_sts |= (1 << PM1_STS_BIT);
}
return generic_sts;
diff --git a/src/soc/intel/apollolake/smihandler.c b/src/soc/intel/apollolake/smihandler.c
index 53d2b7e..424d66f 100644
--- a/src/soc/intel/apollolake/smihandler.c
+++ b/src/soc/intel/apollolake/smihandler.c
@@ -38,19 +38,19 @@
uint32_t smihandler_soc_get_sci_mask(void)
{
uint32_t sci_mask =
- SMI_HANDLER_SCI_EN(APM_SMI_STS) |
- SMI_HANDLER_SCI_EN(SLP_SMI_STS);
+ SMI_HANDLER_SCI_EN(APM_STS_BIT) |
+ SMI_HANDLER_SCI_EN(SMI_ON_SLP_EN_STS_BIT);
return sci_mask;
}
const smi_handler_t southbridge_smi[32] = {
- [SLP_SMI_STS] = smihandler_southbridge_sleep,
- [APM_SMI_STS] = smihandler_southbridge_apmc,
- [FAKE_PM1_SMI_STS] = smihandler_southbridge_pm1,
- [GPIO_SMI_STS] = smihandler_southbridge_gpi,
- [TCO_SMI_STS] = smihandler_southbridge_tco,
- [PERIODIC_SMI_STS] = smihandler_southbridge_periodic,
+ [SMI_ON_SLP_EN_STS_BIT] = smihandler_southbridge_sleep,
+ [APM_STS_BIT] = smihandler_southbridge_apmc,
+ [PM1_STS_BIT] = smihandler_southbridge_pm1,
+ [GPIO_STS_BIT] = smihandler_southbridge_gpi,
+ [TCO_STS_BIT] = smihandler_southbridge_tco,
+ [PERIODIC_STS_BIT] = smihandler_southbridge_periodic,
#if CONFIG(SOC_ESPI)
[ESPI_SMI_STS_BIT] = smihandler_southbridge_espi,
#endif
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