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3 comments:

• File src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/mtthrcSeedTrain.c:

  • Patch Set #2, Line 329: if ((RxEn >= NBPtr->MinRxEnSeedGross) && (RxEn <= NBPtr->MaxRxEnSeedTotal)) {

    Sources had one static initializer for right-hand side of comparison, so those could get treated as […]

    Ack

  • Patch Set #2, Line 337: OutOfRange[ByteLane] = TRUE;

    This path is why I was wondering if the intent with 'PassTestRxEnDly[ByteLane] = RxOrig[ByteLane];' […]

    Further reading shows the passing results are intended to be the only ones considered, so the contents should not matter in a failed case like this. However, it should be initialized regardless. Objection to my moving 'PassTestRxEnDly[ByteLane] = RxOrig[ByteLane];' here?

  • Patch Set #2, Line 359: MemClkCycle = (UINT8) (PassTestRxEnDly[ByteLane] >> 5);

    Is the file run through preprocessor before coverity analysis? IDS_HDT_CONSOLE() may just have empty […]

    Ack

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