Marvin Drees has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49019 )
Change subject: mb/asus/sklkbl_h: Move files from H110T ......................................................................
mb/asus/sklkbl_h: Move files from H110T
Work in Progress.
Change-Id: I3691c5cfd33638f24047ba7912afb55302209198 Signed-off-by: Marvin Drees marvin@ceres-sys.de --- A src/mainboard/asus/sklkbl_h/Kconfig A src/mainboard/asus/sklkbl_h/Kconfig.name A src/mainboard/asus/sklkbl_h/Makefile.inc A src/mainboard/asus/sklkbl_h/acpi/dptf.asl A src/mainboard/asus/sklkbl_h/acpi/ec.asl A src/mainboard/asus/sklkbl_h/acpi/superio.asl A src/mainboard/asus/sklkbl_h/board_info.txt A src/mainboard/asus/sklkbl_h/bootblock.c A src/mainboard/asus/sklkbl_h/cmos.default A src/mainboard/asus/sklkbl_h/cmos.layout A src/mainboard/asus/sklkbl_h/devicetree.cb A src/mainboard/asus/sklkbl_h/dsdt.asl A src/mainboard/asus/sklkbl_h/fadt.c A src/mainboard/asus/sklkbl_h/include/mainboard/gpio.h A src/mainboard/asus/sklkbl_h/mainboard.c A src/mainboard/asus/sklkbl_h/romstage.c A src/mainboard/asus/sklkbl_h/variants/h110t/board_info.txt A src/mainboard/asus/sklkbl_h/variants/h110t/data.vbt A src/mainboard/asus/sklkbl_h/variants/h110t/gma-mainboard.ads A src/mainboard/asus/sklkbl_h/variants/h110t/gpio.c A src/mainboard/asus/sklkbl_h/variants/h110t/gpio_early.c A src/mainboard/asus/sklkbl_h/variants/h110t/hda_verb.c A src/mainboard/asus/sklkbl_h/variants/h110t/overridetree.cb 23 files changed, 1,135 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/49019/1
diff --git a/src/mainboard/asus/sklkbl_h/Kconfig b/src/mainboard/asus/sklkbl_h/Kconfig new file mode 100644 index 0000000..8d8bcd9 --- /dev/null +++ b/src/mainboard/asus/sklkbl_h/Kconfig @@ -0,0 +1,57 @@ +config BOARD_ASUS_SKYLAKE_KABYLAKE + def_bool n + select BOARD_ROMSIZE_KB_16384 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_CMOS_DEFAULT + select HAVE_OPTION_TABLE + select INTEL_GMA_HAVE_VBT + select INTEL_INT15 + select MAINBOARD_HAS_LPC_TPM + select MAINBOARD_USES_IFD_GBE_REGION + select SKYLAKE_SOC_PCH_H + select SOC_INTEL_KABYLAKE + select SUPERIO_NUVOTON_COMMON_COM_A + select SUPERIO_NUVOTON_NCT5539D + select REALTEK_8168_RESET + select RT8168_SET_LED_MODE + +if BOARD_ASUS_SKYLAKE_KABYLAKE + +config MAINBOARD_FAMILY + string + default "Asus_Skylake_Kabylake" + +config MAINBOARD_PART_NUMBER + string + default "H110T" if BOARD_ASUS_H110T + +config MAINBOARD_DIR + string + default "asus/sklkbl_h" + +config VARIANT_DIR + string + default "h110t" if BOARD_ASUS_H110T + +config OVERRIDE_DEVICETREE + string + default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb" + +config IRQ_SLOT_COUNT + int + default 18 + +config MAX_CPUS + int + default 8 + +config DIMM_MAX + int + default 2 if BOARD_ASUS_H110T + +config DIMM_SPD_SIZE + int + default 512 + +endif # BOARD_ASUS_SKYLAKE_KABYLAKE diff --git a/src/mainboard/asus/sklkbl_h/Kconfig.name b/src/mainboard/asus/sklkbl_h/Kconfig.name new file mode 100644 index 0000000..9163d9b --- /dev/null +++ b/src/mainboard/asus/sklkbl_h/Kconfig.name @@ -0,0 +1,3 @@ +config BOARD_ASUS_H110T + bool "H110T" + select BOARD_ASUS_SKYLAKE_KABYLAKE diff --git a/src/mainboard/asus/sklkbl_h/Makefile.inc b/src/mainboard/asus/sklkbl_h/Makefile.inc new file mode 100644 index 0000000..6855b24 --- /dev/null +++ b/src/mainboard/asus/sklkbl_h/Makefile.inc @@ -0,0 +1,12 @@ +## SPDX-License-Identifier: GPL-2.0-only + +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include + +bootblock-y += bootblock.c +bootblock-y += variants/$(VARIANT_DIR)/gpio_early.c + +ramstage-y += mainboard.c +ramstage-y += variants/$(VARIANT_DIR)/gpio.c +ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c +ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainboard.ads diff --git a/src/mainboard/asus/sklkbl_h/acpi/dptf.asl b/src/mainboard/asus/sklkbl_h/acpi/dptf.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/asus/sklkbl_h/acpi/dptf.asl diff --git a/src/mainboard/asus/sklkbl_h/acpi/ec.asl b/src/mainboard/asus/sklkbl_h/acpi/ec.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/asus/sklkbl_h/acpi/ec.asl diff --git a/src/mainboard/asus/sklkbl_h/acpi/superio.asl b/src/mainboard/asus/sklkbl_h/acpi/superio.asl new file mode 100644 index 0000000..800e80a --- /dev/null +++ b/src/mainboard/asus/sklkbl_h/acpi/superio.asl @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#define SUPERIO_DEV SIO0 +#define SUPERIO_PNP_BASE 0x2e +#define NCT5539D_SHOW_SP1 +#define NCT5539D_SHOW_KBC +#define NCT5539D_SHOW_HWM + +#undef NCT5539D_SHOW_GPIO diff --git a/src/mainboard/asus/sklkbl_h/board_info.txt b/src/mainboard/asus/sklkbl_h/board_info.txt new file mode 100644 index 0000000..ba2c1a3 --- /dev/null +++ b/src/mainboard/asus/sklkbl_h/board_info.txt @@ -0,0 +1,2 @@ +Category: desktop +Vendor name: Asus diff --git a/src/mainboard/asus/sklkbl_h/bootblock.c b/src/mainboard/asus/sklkbl_h/bootblock.c new file mode 100644 index 0000000..b2b9564 --- /dev/null +++ b/src/mainboard/asus/sklkbl_h/bootblock.c @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> +#include <mainboard/gpio.h> +#include <superio/nuvoton/common/nuvoton.h> +#include <superio/nuvoton/nct5539d/nct5539d.h> +#include <console/uart.h> + +static void early_config_superio(void) +{ + const pnp_devfn_t serial_dev = PNP_DEV(0x2e, NCT5539D_SP1); + nuvoton_enable_serial(serial_dev, CONFIG_TTYS0_BASE); +} + +void bootblock_mainboard_early_init(void) +{ + mainboard_early_config_gpios(); + early_config_superio(); +} diff --git a/src/mainboard/asus/sklkbl_h/cmos.default b/src/mainboard/asus/sklkbl_h/cmos.default new file mode 100644 index 0000000..f3330e5 --- /dev/null +++ b/src/mainboard/asus/sklkbl_h/cmos.default @@ -0,0 +1,3 @@ +boot_option=Fallback +debug_level=Debug +power_on_after_fail=Disable diff --git a/src/mainboard/asus/sklkbl_h/cmos.layout b/src/mainboard/asus/sklkbl_h/cmos.layout new file mode 100644 index 0000000..454bf10 --- /dev/null +++ b/src/mainboard/asus/sklkbl_h/cmos.layout @@ -0,0 +1,56 @@ +## SPDX-License-Identifier: GPL-2.0-only + +# ----------------------------------------------------------------- +entries + +#start-bit length config config-ID name +0 120 r 0 reserved_memory + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter + +# ----------------------------------------------------------------- +# coreboot config options: console +395 4 e 6 debug_level + +# ----------------------------------------------------------------- +# coreboot config options: cpu +400 1 e 2 hyper_threading + +# ----------------------------------------------------------------- +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +# ----------------------------------------------------------------- +checksums + +checksum 392 415 984 diff --git a/src/mainboard/asus/sklkbl_h/devicetree.cb b/src/mainboard/asus/sklkbl_h/devicetree.cb new file mode 100644 index 0000000..ff58ecf --- /dev/null +++ b/src/mainboard/asus/sklkbl_h/devicetree.cb @@ -0,0 +1,93 @@ +## SPDX-License-Identifier: GPL-2.0-only + +chip soc/intel/skylake + + # FSP Configuration + register "PrimaryDisplay" = "Auto" + register "SaGv" = "SaGv_Enabled" + + # LPC + register "serirq_mode" = "SERIRQ_CONTINUOUS" + + # Enabling SLP_S0, SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch + register "s0ix_enable" = "1" + register "PmConfigSlpS3MinAssert" = "SLP_S3_MIN_ASSERT_50MS" + register "PmConfigSlpS4MinAssert" = "SLP_S4_MIN_ASSERT_4S" + register "PmConfigSlpSusMinAssert" = "SLP_SUS_MIN_ASSERT_4S" + register "PmConfigSlpAMinAssert" = "SLP_A_MIN_ASSERT_2S" + + # Lock Down + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + }" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 01.0 off end # CPU PCIe Port 10 (x16) + device pci 01.1 off end # CPU PCIe Port 11 (x8) + device pci 01.2 off end # CPU PCIe Port 12 (x4) + device pci 02.0 off end # Integrated Graphics Device (IGD) + device pci 04.0 off end # SA thermal subsystem + device pci 05.0 off end # Imaging Unit + device pci 08.0 off end # Gaussion Mixture Model (GMM) + device pci 13.0 off end # Integrated Sensor Hub + device pci 14.0 off end # USB xHCI + device pci 14.1 off end # USB xDCI (OTG) + device pci 14.2 off end # Thermal Subsystem + device pci 15.0 off end # I2C #0 + device pci 15.1 off end # I2C #1 + device pci 15.2 off end # I2C #2 + device pci 15.3 off end # I2C #3 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 17.0 on end # SATA + device pci 19.0 off end # UART #2 + device pci 19.1 off end # I2C #5 + device pci 19.2 off end # I2C #4 + device pci 1b.0 off end # PCH PCIe Port 17 + device pci 1b.1 off end # PCH PCIe Port 18 + device pci 1b.2 off end # PCH PCIe Port 19 + device pci 1b.3 off end # PCH PCIe Port 20 + device pci 1c.0 off end # PCH PCIe Port 1 + device pci 1c.1 off end # PCH PCIe Port 2 + device pci 1c.2 off end # PCH PCIe Port 3 + device pci 1c.3 off end # PCH PCIe Port 4 + device pci 1c.4 off end # PCH PCIe Port 5 + device pci 1c.5 off end # PCH PCIe Port 6 + device pci 1c.6 off end # PCH PCIe Port 7 + device pci 1c.7 off end # PCH PCIe Port 8 + device pci 1d.0 off end # PCH PCIe Port 9 + device pci 1d.1 off end # PCH PCIe Port 10 + device pci 1d.2 off end # PCH PCIe Port 11 + device pci 1d.3 off end # PCH PCIe Port 12 + device pci 1d.4 off end # PCH PCIe Port 13 + device pci 1d.5 off end # PCH PCIe Port 14 + device pci 1d.6 off end # PCH PCIe Port 15 + device pci 1d.7 off end # PCH PCIe Port 16 + device pci 1e.0 off end # UART #0 + device pci 1e.1 off end # UART #1 + device pci 1e.2 off end # SPI #0 + device pci 1e.6 off end # SDXC + device pci 1f.0 on # LPC Interface + chip superio/common + device pnp 2e.0 on end + end + chip drivers/pc80/tpm # TPM + device pnp 0c31.0 off end + end + end + device pci 1f.1 off end # P2SB + device pci 1f.2 on end # Power Management Controller + device pci 1f.3 off end # Intel HDA + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # SPI Controller + device pci 1f.6 off end # GbE + device pci 1f.7 off end # Intel Trace Hub + end +end diff --git a/src/mainboard/asus/sklkbl_h/dsdt.asl b/src/mainboard/asus/sklkbl_h/dsdt.asl new file mode 100644 index 0000000..e84aa1c --- /dev/null +++ b/src/mainboard/asus/sklkbl_h/dsdt.asl @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 /* OEM revision */ +) +{ + #include <soc/intel/common/acpi/platform.asl> + #include <soc/intel/skylake/acpi/globalnvs.asl> + #include <cpu/intel/common/acpi/cpu.asl> + + Scope (_SB) { + Device (PCI0) + { + #include <soc/intel/skylake/acpi/systemagent.asl> + #include <soc/intel/skylake/acpi/pch.asl> + } + + /* Dynamic Platform Thermal Framework */ + #include "acpi/dptf.asl" + } + + #include <southbridge/intel/common/acpi/sleepstates.asl> +} diff --git a/src/mainboard/asus/sklkbl_h/fadt.c b/src/mainboard/asus/sklkbl_h/fadt.c new file mode 100644 index 0000000..b3cf708 --- /dev/null +++ b/src/mainboard/asus/sklkbl_h/fadt.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +#include <soc/acpi.h> + +void mainboard_fill_fadt(acpi_fadt_t *fadt) +{ + fadt->preferred_pm_profile = PM_DESKTOP; +} diff --git a/src/mainboard/asus/sklkbl_h/include/mainboard/gpio.h b/src/mainboard/asus/sklkbl_h/include/mainboard/gpio.h new file mode 100644 index 0000000..3222cd3 --- /dev/null +++ b/src/mainboard/asus/sklkbl_h/include/mainboard/gpio.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +void mainboard_early_config_gpios(void); +void mainboard_config_gpios(void); + +#endif diff --git a/src/mainboard/asus/sklkbl_h/mainboard.c b/src/mainboard/asus/sklkbl_h/mainboard.c new file mode 100644 index 0000000..b857592 --- /dev/null +++ b/src/mainboard/asus/sklkbl_h/mainboard.c @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <device/device.h> +#include <drivers/intel/gma/int15.h> +#include <mainboard/gpio.h> + +static void init_mainboard(void *chip_info) +{ + mainboard_config_gpios(); +} + +static void enable_mainboard(struct device *dev) +{ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE, GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +} + +struct chip_operations mainboard_ops = { + .init = init_mainboard, + .enable_dev = enable_mainboard, +}; diff --git a/src/mainboard/asus/sklkbl_h/romstage.c b/src/mainboard/asus/sklkbl_h/romstage.c new file mode 100644 index 0000000..7c532e4 --- /dev/null +++ b/src/mainboard/asus/sklkbl_h/romstage.c @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <assert.h> +#include <soc/romstage.h> +#include <stdint.h> +#include <string.h> +#include <spd_bin.h> + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + const u16 rcomp_resistors[3] = {121, 75, 100}; + + const u16 rcomp_targets[5] = {50, 26, 20, 20, 26}; + + FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig; + + struct spd_block blk = { + .addr_map = {0x50, 0x52}, + }; + + assert(sizeof(mem_cfg->RcompResistor) == sizeof(rcomp_resistors)); + assert(sizeof(mem_cfg->RcompTarget) == sizeof(rcomp_targets)); + + mem_cfg->DqPinsInterleaved = 1; + get_spd_smbus(&blk); + mem_cfg->MemorySpdDataLen = blk.len; + mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0]; + mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[1]; + dump_spd_info(&blk); + + memcpy(mem_cfg->RcompResistor, rcomp_resistors, sizeof(mem_cfg->RcompResistor)); + memcpy(mem_cfg->RcompTarget, rcomp_targets, sizeof(mem_cfg->RcompTarget)); + + /* use virtual channel 1 for the dmi interface of the PCH */ + mupd->FspmTestConfig.DmiVc1 = 1; + + /* desktop type */ + mem_cfg->UserBd = BOARD_TYPE_DESKTOP; +} diff --git a/src/mainboard/asus/sklkbl_h/variants/h110t/board_info.txt b/src/mainboard/asus/sklkbl_h/variants/h110t/board_info.txt new file mode 100644 index 0000000..7387277 --- /dev/null +++ b/src/mainboard/asus/sklkbl_h/variants/h110t/board_info.txt @@ -0,0 +1,9 @@ +Category: desktop +Vendor name: Asus +Board name: H110T +Board URL: https://www.asus.com/Motherboards/H110T/ +ROM package: DIP-8 +ROM protocol: SPI +ROM socketed: y +Flashrom support: y +Release year: 2016 diff --git a/src/mainboard/asus/sklkbl_h/variants/h110t/data.vbt b/src/mainboard/asus/sklkbl_h/variants/h110t/data.vbt new file mode 100644 index 0000000..0061c69 --- /dev/null +++ b/src/mainboard/asus/sklkbl_h/variants/h110t/data.vbt Binary files differ diff --git a/src/mainboard/asus/sklkbl_h/variants/h110t/gma-mainboard.ads b/src/mainboard/asus/sklkbl_h/variants/h110t/gma-mainboard.ads new file mode 100644 index 0000000..ee6553d --- /dev/null +++ b/src/mainboard/asus/sklkbl_h/variants/h110t/gma-mainboard.ads @@ -0,0 +1,17 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (HDMI1, + DP1, + LVDS, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/asus/sklkbl_h/variants/h110t/gpio.c b/src/mainboard/asus/sklkbl_h/variants/h110t/gpio.c new file mode 100644 index 0000000..a3d890c --- /dev/null +++ b/src/mainboard/asus/sklkbl_h/variants/h110t/gpio.c @@ -0,0 +1,536 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <mainboard/gpio.h> +#include <soc/gpe.h> +#include <soc/gpio.h> + +static const struct pad_config gpio_table[] = { + + /* ------- GPIO Community 0 ------- */ + + /* ------- GPIO Group GPP_A ------- */ + _PAD_CFG_STRUCT(GPP_A0, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* RCIN# */ + _PAD_CFG_STRUCT(GPP_A1, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | (1 << 1), PAD_PULL(UP_20K)), /* LAD0 */ + _PAD_CFG_STRUCT(GPP_A2, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | (1 << 1), PAD_PULL(UP_20K)), /* LAD1 */ + _PAD_CFG_STRUCT(GPP_A3, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | (1 << 1), PAD_PULL(UP_20K)), /* LAD2 */ + _PAD_CFG_STRUCT(GPP_A4, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | (1 << 1), PAD_PULL(UP_20K)), /* LAD3 */ + _PAD_CFG_STRUCT(GPP_A5, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), /* LFRAME# */ + _PAD_CFG_STRUCT(GPP_A6, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF), 0), /* SERIRQ */ + _PAD_CFG_STRUCT(GPP_A7, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_A8, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), /* CLKRUN# */ + _PAD_CFG_STRUCT(GPP_A9, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), PAD_PULL(DN_20K)), /* CLKOUT_LPC0 */ + _PAD_CFG_STRUCT(GPP_A10, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), PAD_PULL(DN_20K)), /* CLKOUT_LPC1 */ + _PAD_CFG_STRUCT(GPP_A11, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), /* PME# */ + _PAD_CFG_STRUCT(GPP_A12, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_A13, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), /* SUSWARN#/SUSPWRDNACK */ + _PAD_CFG_STRUCT(GPP_A14, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_A15, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), PAD_PULL(UP_20K)), /* SUS_ACK# */ + _PAD_CFG_STRUCT(GPP_A16, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_A17, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_A18, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_A19, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + PAD_CFG_GPO(GPP_A20, 0, PLTRST), /* GPIO */ + _PAD_CFG_STRUCT(GPP_A21, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_A22, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_A23, NONE, PLTRST, OFF, ACPI), /* GPIO */ + + /* ------- GPIO Group GPP_B ------- */ + _PAD_CFG_STRUCT(GPP_B0, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B1, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B2, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B3, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B4, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_B5, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_B6, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_B7, NONE, PLTRST, OFF, ACPI), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B8, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B9, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B10, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B11, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B12, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B13, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), + 0), /* PLTRST# */ + _PAD_CFG_STRUCT(GPP_B14, + PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), + PAD_PULL(DN_20K)), /* SPKR */ + _PAD_CFG_STRUCT(GPP_B15, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + PAD_CFG_GPO(GPP_B16, 0, PLTRST), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B17, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B18, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B19, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B20, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B21, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B22, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B23, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + + /* ------- GPIO Community 1 ------- */ + + /* ------- GPIO Group GPP_C ------- */ + _PAD_CFG_STRUCT(GPP_C0, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) + | (1 << 1), + 0), /* SMBCLK */ + _PAD_CFG_STRUCT(GPP_C1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | (1 << 1), + 0), /* SMBDATA */ + _PAD_CFG_STRUCT(GPP_C2, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_C3, + PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) + | (1 << 1), + 0), /* SML0CLK */ + _PAD_CFG_STRUCT(GPP_C4, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | (1 << 1), + 0), /* SML0DATA */ + _PAD_CFG_STRUCT(GPP_C5, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_C6, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_C7, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_C8, NONE, PLTRST, OFF, ACPI), /* GPIO */ + _PAD_CFG_STRUCT(GPP_C9, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_C10, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_C11, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_C12, NONE, PLTRST, OFF, ACPI), /* GPIO */ + _PAD_CFG_STRUCT(GPP_C13, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_C14, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_C15, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_C16, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_C17, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_C18, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_C19, NONE, PLTRST, OFF, ACPI), /* GPIO */ + _PAD_CFG_STRUCT(GPP_C20, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_C21, NONE, PLTRST, OFF, ACPI), /* GPIO */ + _PAD_CFG_STRUCT(GPP_C22, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(SCI) + | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_C23, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(SCI) + | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 1), + 0), /* GPIO */ + + /* ------- GPIO Group GPP_D ------- */ + _PAD_CFG_STRUCT(GPP_D0, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_D1, NONE, PLTRST, OFF, ACPI), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D2, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D3, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D4, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(SCI) + | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 1), + 0), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_D5, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_D6, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_D7, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_D8, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_D9, DN_20K, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_D10, DN_20K, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_D11, DN_20K, RSMRST, OFF, ACPI), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D12, + PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + PAD_PULL(DN_20K)), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_D13, NONE, PLTRST, OFF, ACPI), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D14, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_D15, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_D16, DN_20K, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_D17, NONE, PLTRST, OFF, ACPI), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D18, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D19, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_D20, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_D21, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_D22, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_D23, NONE, PLTRST, OFF, ACPI), /* GPIO */ + + /* ------- GPIO Group GPP_E ------- */ + PAD_CFG_GPI_TRIG_OWN(GPP_E0, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_E1, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_E2, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_E3, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_E4, NONE, DEEP, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_E5, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_E6, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_E7, NONE, PLTRST, OFF, ACPI), /* GPIO */ + _PAD_CFG_STRUCT(GPP_E8, + PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), + 0), /* SATA_LED# */ + _PAD_CFG_STRUCT(GPP_E9, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* USB_OC0# */ + _PAD_CFG_STRUCT(GPP_E10, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* USB_OC1# */ + _PAD_CFG_STRUCT(GPP_E11, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* USB_OC2# */ + _PAD_CFG_STRUCT(GPP_E12, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* USB_OC3# */ + + /* ------- GPIO Group GPP_F ------- */ + _PAD_CFG_STRUCT(GPP_F0, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F1, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + PAD_PULL(UP_20K)), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F2, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + PAD_PULL(UP_20K)), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F3, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F4, NONE, PLTRST, OFF, ACPI), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F5, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F6, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F7, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F8, NONE, PLTRST, OFF, ACPI), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F9, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F10, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F11, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F12, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F13, NONE, PLTRST, OFF, ACPI), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F14, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F15, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* USB_OC4# */ + _PAD_CFG_STRUCT(GPP_F16, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F17, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F18, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F19, + PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), + 0), /* eDP_VDDEN */ + _PAD_CFG_STRUCT(GPP_F20, + PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), + 0), /* eDP_BKLTEN */ + _PAD_CFG_STRUCT(GPP_F21, + PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), + 0), /* eDP_BKLTCTL */ + PAD_CFG_GPI_TRIG_OWN(GPP_F22, NONE, PLTRST, OFF, ACPI), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F23, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + + /* ------- GPIO Group GPP_G ------- */ + _PAD_CFG_STRUCT(GPP_G0, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_G1, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_G2, DN_20K, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_G3, DN_20K, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_G4, DN_20K, RSMRST, OFF, ACPI), /* GPIO */ + _PAD_CFG_STRUCT(GPP_G5, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_G6, NONE, PLTRST, OFF, ACPI), /* GPIO */ + _PAD_CFG_STRUCT(GPP_G7, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_G8, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_G9, NONE, PLTRST, OFF, ACPI), /* GPIO */ + _PAD_CFG_STRUCT(GPP_G10, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_G11, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_G12, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_G13, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_G14, NONE, PLTRST, OFF, ACPI), /* GPIO */ + _PAD_CFG_STRUCT(GPP_G15, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_G16, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_G17, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_G18, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_G19, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_G20, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_G21, NONE, PLTRST, OFF, ACPI), /* GPIO */ + _PAD_CFG_STRUCT(GPP_G22, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_G23, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + + /* ------- GPIO Group GPP_H ------- */ + PAD_CFG_GPI_TRIG_OWN(GPP_H0, NONE, PLTRST, OFF, ACPI), /* GPIO */ + _PAD_CFG_STRUCT(GPP_H1, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) + | (1 << 1), + 0), /* SRCCLKREQ7# */ + PAD_CFG_GPI_TRIG_OWN(GPP_H2, NONE, PLTRST, OFF, ACPI), /* GPIO */ + _PAD_CFG_STRUCT(GPP_H3, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_H4, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_H5, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_H6, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_H7, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_H8, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_H9, NONE, PLTRST, OFF, ACPI), /* GPIO */ + _PAD_CFG_STRUCT(GPP_H10, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_H11, NONE, PLTRST, OFF, ACPI), /* GPIO */ + _PAD_CFG_STRUCT(GPP_H12, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_H13, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_H14, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_H15, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_H16, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_H17, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_H18, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_H19, NONE, PLTRST, OFF, ACPI), /* GPIO */ + _PAD_CFG_STRUCT(GPP_H20, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_H21, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_H22, NONE, PLTRST, OFF, ACPI), /* GPIO */ + _PAD_CFG_STRUCT(GPP_H23, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + + /* ------- GPIO Community 2 ------- */ + + /* -------- GPIO Group GPD -------- */ + _PAD_CFG_STRUCT(GPD0, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPD1, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPD2, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), + 0), /* LAN_WAKE# */ + _PAD_CFG_STRUCT(GPD3, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), + PAD_PULL(UP_20K)), /* PWRBTN# */ + _PAD_CFG_STRUCT(GPD4, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), + 0), /* SLP_S3# */ + _PAD_CFG_STRUCT(GPD5, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), + 0), /* SLP_S4# */ + _PAD_CFG_STRUCT(GPD6, PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPD7, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1) | 1, + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPD8, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPD9, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPD10, PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), + 0), /* GPIO */ + _PAD_CFG_STRUCT(GPD11, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), + 0), /* LANPHYPC */ + + /* ------- GPIO Community 3 ------- */ + + /* ------- GPIO Group GPP_I ------- */ + _PAD_CFG_STRUCT(GPP_I0, + PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), + 0), /* DDPB_HPD0 */ + _PAD_CFG_STRUCT(GPP_I1, + PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* DDPC_HPD1 */ + _PAD_CFG_STRUCT(GPP_I2, + PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), + 0), /* DDPD_HPD2 */ + _PAD_CFG_STRUCT(GPP_I3, + PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* DDPE_HPD3 */ + _PAD_CFG_STRUCT(GPP_I4, + PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* EDP_HPD */ + _PAD_CFG_STRUCT(GPP_I5, + PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), + 0), /* DDPB_CTRLCLK */ + _PAD_CFG_STRUCT(GPP_I6, + PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), + PAD_PULL(DN_20K)), /* DDPB_CTRLDATA */ + _PAD_CFG_STRUCT(GPP_I7, + PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), + 0), /* DDPC_CTRLCLK */ + _PAD_CFG_STRUCT(GPP_I8, + PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), + PAD_PULL(DN_20K)), /* DDPC_CTRLDATA */ + _PAD_CFG_STRUCT(GPP_I9, + PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + 0), /* DDPD_CTRLCLK */ + _PAD_CFG_STRUCT(GPP_I10, + PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) + | (1 << 1), + PAD_PULL(DN_20K)), /* DDPD_CTRLDATA */ +}; + +void mainboard_config_gpios(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/asus/sklkbl_h/variants/h110t/gpio_early.c b/src/mainboard/asus/sklkbl_h/variants/h110t/gpio_early.c new file mode 100644 index 0000000..0f10665 --- /dev/null +++ b/src/mainboard/asus/sklkbl_h/variants/h110t/gpio_early.c @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <mainboard/gpio.h> +#include <soc/gpio.h> + +static const struct pad_config early_gpio_table[] = { + /* Early LPC configuration in romstage */ + _PAD_CFG_STRUCT(GPP_A0, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* RCIN# */ + _PAD_CFG_STRUCT(GPP_A1, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | (1 << 1), PAD_PULL(UP_20K)), /* LAD0 */ + _PAD_CFG_STRUCT(GPP_A2, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | (1 << 1), PAD_PULL(UP_20K)), /* LAD1 */ + _PAD_CFG_STRUCT(GPP_A3, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | (1 << 1), PAD_PULL(UP_20K)), /* LAD2 */ + _PAD_CFG_STRUCT(GPP_A4, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | (1 << 1), PAD_PULL(UP_20K)), /* LAD3 */ + _PAD_CFG_STRUCT(GPP_A5, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), /* LFRAME# */ + _PAD_CFG_STRUCT(GPP_A6, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF), 0), /* SERIRQ */ + _PAD_CFG_STRUCT(GPP_A7, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_A8, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), /* CLKRUN# */ + _PAD_CFG_STRUCT(GPP_A9, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), PAD_PULL(DN_20K)), /* CLKOUT_LPC0 */ + _PAD_CFG_STRUCT(GPP_A10, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), PAD_PULL(DN_20K)), /* CLKOUT_LPC1 */ + _PAD_CFG_STRUCT(GPP_A11, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), /* PME# */ + _PAD_CFG_STRUCT(GPP_A12, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_A13, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), /* SUSWARN#/SUSPWRDNACK */ + _PAD_CFG_STRUCT(GPP_A14, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_A15, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), PAD_PULL(UP_20K)), /* SUS_ACK# */ + }; + +void mainboard_early_config_gpios(void) +{ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} diff --git a/src/mainboard/asus/sklkbl_h/variants/h110t/hda_verb.c b/src/mainboard/asus/sklkbl_h/variants/h110t/hda_verb.c new file mode 100644 index 0000000..136c60a --- /dev/null +++ b/src/mainboard/asus/sklkbl_h/variants/h110t/hda_verb.c @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0887, /* Codec Vendor / Device ID: Realtek ALC887 */ + 0x10438445, /* Subsystem ID */ + 15, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x10438445), + AZALIA_PIN_CFG(0, 0x11, 0x40000000), + AZALIA_PIN_CFG(0, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0, 0x14, 0x01014020), + AZALIA_PIN_CFG(0, 0x15, 0x90170110), + AZALIA_PIN_CFG(0, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x01a19040), + AZALIA_PIN_CFG(0, 0x19, 0x02a19050), + AZALIA_PIN_CFG(0, 0x1a, 0x0181304f), + AZALIA_PIN_CFG(0, 0x1b, 0x02214030), + AZALIA_PIN_CFG(0, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x4026c629), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1f, 0x411111f0), + + 0x80862809, /* Codec Vendor / Device ID: Intel Skylake HDMI */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(2, 0x80860101), + AZALIA_PIN_CFG(2, 0x05, 0x18560010), + AZALIA_PIN_CFG(2, 0x06, 0x18560020), + AZALIA_PIN_CFG(2, 0x07, 0x18560030), +}; + +const u32 pc_beep_verbs[] = {}; +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/asus/sklkbl_h/variants/h110t/overridetree.cb b/src/mainboard/asus/sklkbl_h/variants/h110t/overridetree.cb new file mode 100644 index 0000000..fd78910 --- /dev/null +++ b/src/mainboard/asus/sklkbl_h/variants/h110t/overridetree.cb @@ -0,0 +1,148 @@ +## SPDX-License-Identifier: GPL-2.0-only + +chip soc/intel/skylake + + register "deep_sx_config" = "DSX_EN_WAKE_PIN" + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "gpe0_dw0" = "GPP_B" + register "gpe0_dw1" = "GPP_D" + register "gpe0_dw2" = "GPP_E" + + # FSP Configuration + register "PrimaryDisplay" = "Display_iGFX" + register "SkipExtGfxScan" = "1" + + # Send an extra VR mailbox command for the PS4 exit issue + register "SendVrMbxCmd" = "2" + + # TODO figure these values out + # USB configuration + # USB 5/6 (header) + #register "usb2_ports[?]" = + #register "usb2_ports[?]" = + # USB 7/8 (header) + #register "usb2_ports[?]" = + #register "usb2_ports[?]" = + # USB 9 (header) + #register "usb2_ports[?]" = + + # USB3 1/2 (rear ports) + #register "usb3_ports[?]" = + #register "usb3_ports[?]" = + + # USB3 3/4 (rear ports) + #register "usb3_ports[?]" = + #register "usb3_ports[?]" = + + # SATA configuration + register "SataSalpSupport" = "1" + register "SataPortsEnable" = "{ + [0] = 1, + [1] = 1, + }" + + # Sound configuration + register "PchHdaVcType" = "Vc1" + + # PCIe configuration + register "PcieRpEnable[0]" = "1" + register "PcieRpEnable[8]" = "1" + register "PcieRpAdvancedErrorReporting[8]" = "1" + register "PcieRpLtrEnable[8]" = "1" + register "PcieRpEnable[9]" = "1" + register "PcieRpAdvancedErrorReporting[9]" = "1" + register "PcieRpLtrEnable[9]" = "1" + + device cpu_cluster 0 on + device lapic 0 on end + end + + device domain 0 on + subsystemid 0x1043 0x8694 inherit + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 14.0 on end # USB xHCI + device pci 14.2 off end # Thermal Subsystem # TODO Maybe needed? + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 # TODO Maybe needed? + device pci 16.4 off end # Management Engine Interface 3 # TODO Maybe needed? + device pci 17.0 on end # SATA + device pci 1c.0 on end # PCI Express Port 5 + device pci 1d.0 on end # PCI Express Port 9 + device pci 1d.1 on end # PCI Express Port 10 - Realtek onboard LAN + device pci 1e.0 off end # UART #0 # TODO Maybe needed? + device pci 1f.0 on # LPC bridge # TODO the superio config probably needs improvement + chip superio/common + device pnp 2e.0 on # passes SIO base addr to SSDT gen + chip superio/nuvoton/nct5539d + device pnp 2e.1 on + irq 0x13 = 0xff + irq 0x14 = 0xff + irq 0x1a = 0x00 + irq 0x24 = 0x00 + irq 0x26 = 0x00 + irq 0x27 = 0x01 + irq 0x28 = 0x10 + irq 0x2a = 0x00 + irq 0x2c = 0x00 + irq 0x2d = 0x02 + irq 0x2f = 0x00 + end + device pnp 2e.2 on # UART A + io 0x60 = 0x03f8 + irq 0x70 = 4 + end + device pnp 2e.5 on # PS/2 KBC + io 0x60 = 0x0060 + io 0x62 = 0x0064 + irq 0x70 = 1 # Keyboard + irq 0x72 = 12 # Mouse + end + device pnp 2e.6 off end # CIR + device pnp 2e.7 off end # GPIO7 + device pnp 2e.107 off end # GPIO8 + device pnp 2e.8 off end # WDT + device pnp 2e.108 off end # GPIO0 + device pnp 2e.308 off end # GPIO BASE + device pnp 2e.408 off end # WDTMEM + device pnp 2e.9 off end # GPIO2 + device pnp 2e.109 off end # GPIO3 + device pnp 2e.209 off end # GPIO4 + device pnp 2e.309 off end # GPIO5 + device pnp 2e.a on # ACPI + irq 0xe6 = 0x0a + irq 0xe7 = 0x11 + irq 0xec = 0x80 + irq 0xf2 = 0x5d + end + device pnp 2e.b on # HWM, LED + io 0x60 = 0x0290 + irq 0xf0 = 0x7e + end + device pnp 2e.d off end # BCLK/WDT2/WDT_MEM + device pnp 2e.e off end # CIR WAKE-UP + device pnp 2e.f off end # GPIO PP/OD + device pnp 2e.14 off end # SVID/PORT 80 + device pnp 2e.16 off end # DS5 + device pnp 2e.116 off end # DS3 + device pnp 2e.316 off end # PCHDSW + device pnp 2e.416 off end # DSWWOPT + device pnp 2e.516 off end # DS3OPT + device pnp 2e.616 off end # DSDSS + device pnp 2e.716 off end # DSPU + end # superio/nuvoton/nct5539d + end # SSDT gen + end # superio/common + end # LPC Interface + device pci 1f.1 off end # P2SB # TODO Maybe needed? + device pci 1f.2 on end # Power Management Controller + device pci 1f.3 on end # Intel HDA + device pci 1f.4 on end # SMBus + device pci 1f.5 off end # PCH SPI # TODO Maybe needed? + device pci 1f.6 on end # GbE + end +end