Patch Set 4:

Are the PTT changes causing the overflow? They really shouldn't, since tegra210 shouldn't have it enabled. How big exactly is the verstage before and after the PTT change?

To be honest - I got no clue. The size of the .elf file is 105300 in both cases. The .debug file is bigger with the VBOOT Changes from the other patch, but still it should have no effect here. Can I safely decrease the size of the CBFS_CACHE from 32 to 30? That would at least solve the problem. Or how can I check the compressed size of the verstage?

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ie00498838a644a6f92881db85833dd0a94b87f53
Gerrit-Change-Number: 34640
Gerrit-PatchSet: 6
Gerrit-Owner: Christian Walter <christian.walter@9elements.com>
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Gerrit-Comment-Date: Thu, 01 Aug 2019 14:19:10 +0000
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