Subrata Banik has uploaded this change for review.
soc/intel/common: Skip SoC GT programming based on CONFIG_SKIP_GRAPHICS_ENABLING
Skip GT specific programming in coreboot to support early
parts without GT enable.
Change-Id: I231e13367cbfbafbfb0cb4235487dbcbcae76820
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
---
M src/soc/intel/common/block/graphics/Kconfig
M src/soc/intel/icelake/graphics.c
2 files changed, 12 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/33189/1
diff --git a/src/soc/intel/common/block/graphics/Kconfig b/src/soc/intel/common/block/graphics/Kconfig
index 4ab9200..36cac22 100644
--- a/src/soc/intel/common/block/graphics/Kconfig
+++ b/src/soc/intel/common/block/graphics/Kconfig
@@ -2,3 +2,11 @@
bool
help
Intel Processor common Graphics support
+
+config SKIP_GRAPHICS_ENABLING
+ bool
+ depends on SOC_INTEL_COMMON_BLOCK_GRAPHICS
+ default n
+ help
+ Skip GT specific programming in coreboot to support
+ early parts without GT enable.
diff --git a/src/soc/intel/icelake/graphics.c b/src/soc/intel/icelake/graphics.c
index 0fbddf0..0709033 100644
--- a/src/soc/intel/icelake/graphics.c
+++ b/src/soc/intel/icelake/graphics.c
@@ -34,6 +34,10 @@
{
uint32_t ddi_buf_ctl;
+ /* Skip IGD GT programming */
+ if (CONFIG(SKIP_GRAPHICS_ENABLING))
+ return;
+
/*
* Enable DDI-A (eDP) 4-lane operation if the link is not up yet.
* This will allow the kernel to use 4-lane eDP links properly
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