mainboard/intel/tgl: Customize PCH VR settings for better Sx power savings

v1p05 and vnn power rails can be used as an alternative source
by-passing vccin_aux during Sx. This by-pass feature, enables us to
shutdown vccin_aux rail which is higher voltage rail compared to v1p05
and vnn. These both rails were disabled by default in FSP. Changes in
this patch are:

1. v1p05 and vnn rails are enabled and enabled supported voltage types
   in S0i1, S0i2, S0i3, S3, S4, S5 states. They were disabled by default.

2. Icc Max for v1p05 changed to 500 mA from default 100 mA.

3. vnn rail's voltage is changed to 5 V from default 4.2 V.

BUG=None
BRANCH=None
TEST="Build and boot TGL-UP3 and check VR settings with Intel ITP-XDP
debugger and verify approx 20mW SoC power savings in S0ix"

Change-Id: Ic889d0952b75a636d2186d81fb679f74d50e7048
Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com>
---
M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
2 files changed, 28 insertions(+), 0 deletions(-)