Subrata Banik has uploaded this change for review.
mb/intel/adlrvp: Remove unused EC_SYNC_IRQ GPIO on ADLRVP
As per latest schematics GPP_A15 is not used for EC_SYNC_IRQ
hence remove the unused GPIO.
Wrong GPIO configuration is causing platform reboot issue on
ADLRVP with Chrome SKU.
Change-Id: I704cd722683258c80197d8872d3bdaafb7c923dc
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
---
M src/mainboard/intel/adlrvp/include/baseboard/ec.h
M src/mainboard/intel/adlrvp/include/baseboard/gpio.h
2 files changed, 0 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/48131/1
diff --git a/src/mainboard/intel/adlrvp/include/baseboard/ec.h b/src/mainboard/intel/adlrvp/include/baseboard/ec.h
index 4303faf..c018299 100644
--- a/src/mainboard/intel/adlrvp/include/baseboard/ec.h
+++ b/src/mainboard/intel/adlrvp/include/baseboard/ec.h
@@ -56,9 +56,6 @@
/* Enable EC backed ALS device in ACPI */
#define EC_ENABLE_ALS_DEVICE
-/* Enable EC sync interrupt, EC_SYNC_IRQ is defined in baseboard/gpio.h */
-#define EC_ENABLE_SYNC_IRQ
-
/* Enable EC backed PD MCU device in ACPI */
#define EC_ENABLE_PD_MCU_DEVICE
diff --git a/src/mainboard/intel/adlrvp/include/baseboard/gpio.h b/src/mainboard/intel/adlrvp/include/baseboard/gpio.h
index b61276c..de0adf6 100644
--- a/src/mainboard/intel/adlrvp/include/baseboard/gpio.h
+++ b/src/mainboard/intel/adlrvp/include/baseboard/gpio.h
@@ -12,7 +12,4 @@
/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */
#define GPE_EC_WAKE GPE0_LAN_WAK
-/* EC sync IRQ */
-#define EC_SYNC_IRQ GPP_A15_IRQ
-
#endif /* __BASEBOARD_GPIO_H__ */
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