Sorry, didn't have time for a full review just now, but saw "picasso" and wanted to comment...
1 comment:
Patch Set #3, Line 51: #define TIMESTAMP_CACHE_IN_BSS (ENV_RAMSTAGE || ENV_POSTCAR)
In its current state this commit enables the follow-ups that would simplify car. […]
It's not an insurmountable problem, but I would prefer initializing timestamps in picasso before cbmem is up. Otherwise my alternative is to keep them noted until cbmem is ready and then initialize TSs. The reason is that we don't know the memory map until after fsp_memory_init() runs. Although FSP-M isn't turning on DRAM, the top of low memory isn't easily discoverable like in Intel -- the hard part is when UMA is <4GB, so we rely on AGESA to report it to us.
Re. PCIe training and enumeration, that's an open question. Definitely not my goal... However IIRC AGESA has always wanted the topology information early, and AMD has still baked in a DEPEX for that info. Right now I don't know whether it's a real dependency or artificial. However, cbmem_top() is valid in romstage. (FWIW, the very first prototype-ish implementation put 100% of functionality into FSP-M, but that was due to a bug that would hang FSP-S if it was runexecuted, so I don't know if that's clouding any perception.)
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