Patrick Georgi submitted this change.
soc/intel/alderlake: Refactor PCIE port config
Refactor PCIE port config structure. Make it easier to map from
schematic. We don't have to convert the PCIE ports RP number and
CLK source in devicetree. All the convert will be done by SoC level.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I0b390e43f8e99b19cfad178139b86a2f77d7a57b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48340
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
---
M src/mainboard/google/brya/variants/baseboard/devicetree.cb
M src/mainboard/intel/adlrvp/devicetree.cb
M src/soc/intel/alderlake/chip.h
M src/soc/intel/alderlake/fsp_params.c
M src/soc/intel/alderlake/romstage/fsp_params.c
5 files changed, 150 insertions(+), 126 deletions(-)
diff --git a/src/mainboard/google/brya/variants/baseboard/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/devicetree.cb
index 51a39c0..647ea42 100644
--- a/src/mainboard/google/brya/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/brya/variants/baseboard/devicetree.cb
@@ -14,42 +14,13 @@
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC3)" # USB3/2 Type A port A0
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 WWAN
- # Enable WLAN PCIE 5 using clk 2
- register "PchPcieRpEnable[5]" = "1"
- register "PcieRpLtrEnable[5]" = "1"
- register "PcieClkSrcUsage[2]" = "5"
- register "PcieClkSrcClkReq[2]" = "2"
- register "PcieRpAdvancedErrorReporting[5]" = "1"
-
- # Enable WWAN PCIE 6 using clk 5
- register "PchPcieRpEnable[6]" = "1"
- register "PcieRpLtrEnable[6]" = "1"
- register "PcieClkSrcUsage[5]" = "6"
- register "PcieClkSrcClkReq[5]" = "5"
- register "PcieRpAdvancedErrorReporting[6]" = "1"
-
- # Enable SD Card PCIE 8 using clk 3
- register "PchPcieRpEnable[7]" = "1"
- register "PcieRpLtrEnable[7]" = "1"
- register "PcieRpHotPlug[7]" = "1"
- register "PcieClkSrcUsage[3]" = "7"
- register "PcieClkSrcClkReq[3]" = "3"
- register "PcieRpAdvancedErrorReporting[7]" = "1"
-
- # Enable NVMe PCIE 9 using clk 1
- register "PchPcieRpEnable[8]" = "1"
- register "PcieRpLtrEnable[8]" = "1"
- register "PcieClkSrcUsage[1]" = "8"
- register "PcieClkSrcClkReq[1]" = "1"
- register "PcieRpAdvancedErrorReporting[8]" = "1"
-
register "SerialIoI2cMode" = "{
- [PchSerialIoIndexI2C0] = PchSerialIoPci,
- [PchSerialIoIndexI2C1] = PchSerialIoPci,
- [PchSerialIoIndexI2C2] = PchSerialIoPci,
- [PchSerialIoIndexI2C3] = PchSerialIoPci,
- [PchSerialIoIndexI2C4] = PchSerialIoPci,
- [PchSerialIoIndexI2C5] = PchSerialIoPci,
+ [PchSerialIoIndexI2C0] = PchSerialIoPci,
+ [PchSerialIoIndexI2C1] = PchSerialIoPci,
+ [PchSerialIoIndexI2C2] = PchSerialIoPci,
+ [PchSerialIoIndexI2C3] = PchSerialIoPci,
+ [PchSerialIoIndexI2C4] = PchSerialIoPci,
+ [PchSerialIoIndexI2C5] = PchSerialIoPci,
}"
register "SerialIoGSpiMode" = "{
@@ -121,10 +92,38 @@
end
device ref heci1 on end
device ref sata on end
- device ref pcie_rp5 on end #PCIE5 WLAN
- device ref pcie_rp6 on end #PCIE6 WWAN
- device ref pcie_rp8 on end #PCIE8 SD card
- device ref pcie_rp9 on end #PCIE9-12 SSD
+ device ref pcie_rp5 on
+ # Enable WLAN PCIE 5 using clk 2
+ register "pch_pcie_rp[PCH_RP(5)]" = "{
+ .clk_src = 2,
+ .clk_req = 2,
+ .flags = PCIE_RP_LTR | PCIE_RP_AER,
+ }"
+ end #PCIE5 WLAN
+ device ref pcie_rp6 on
+ # Enable WWAN PCIE 6 using clk 5
+ register "pch_pcie_rp[PCH_RP(6)]" = "{
+ .clk_src = 5,
+ .clk_req = 5,
+ .flags = PCIE_RP_LTR | PCIE_RP_AER,
+ }"
+ end #PCIE6 WWAN
+ device ref pcie_rp8 on
+ # Enable SD Card PCIE 8 using clk 3
+ register "pch_pcie_rp[PCH_RP(8)]" = "{
+ .clk_src = 3,
+ .clk_req = 3,
+ .flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR | PCIE_RP_AER,
+ }"
+ end #PCIE8 SD card
+ device ref pcie_rp9 on
+ # Enable NVMe PCIE 9 using clk 1
+ register "pch_pcie_rp[PCH_RP(9)]" = "{
+ .clk_src = 1,
+ .clk_req = 1,
+ .flags = PCIE_RP_LTR | PCIE_RP_AER,
+ }"
+ end #PCIE9-12 SSD
device ref uart0 on end
device ref gspi1 on end
device ref pch_espi on
diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb
index 0dd1456..eb7be69 100644
--- a/src/mainboard/intel/adlrvp/devicetree.cb
+++ b/src/mainboard/intel/adlrvp/devicetree.cb
@@ -40,49 +40,58 @@
register "PrmrrSize" = "0"
# Enable PCH PCIE RP 5 using CLK 2
- register "PchPcieRpEnable[4]" = "1"
- register "PcieClkSrcClkReq[2]" = "2"
- register "PcieClkSrcUsage[2]" = "0x4"
- register "PcieRpClkReqDetect[4]" = "1"
+ register "pch_pcie_rp[PCH_RP(5)]" = "{
+ .clk_src = 2,
+ .clk_req = 2,
+ .flags = PCIE_RP_CLK_REQ_DETECT,
+ }"
# Enable PCH PCIE RP 6 using CLK 5
- register "PchPcieRpEnable[5]" = "1"
- register "PcieClkSrcClkReq[5]" = "5"
- register "PcieClkSrcUsage[5]" = "0x5"
- register "PcieRpClkReqDetect[5]" = "1"
+ register "pch_pcie_rp[PCH_RP(6)]" = "{
+ .clk_src = 5,
+ .clk_req = 5,
+ .flags = PCIE_RP_CLK_REQ_DETECT,
+ }"
- # Enable PCH PCIE RP 8 using CLK 6
- register "PchPcieRpEnable[7]" = "1"
- register "PcieClkSrcUsage[6]" = "PCIE_CLK_FREE" # CLK 6 is using free running CLK
+ # Enable PCH PCIE RP 8 using free running CLK (0x80)
+ # Clock source is shared with LAN and hence marked as free running.
+ register "pch_pcie_rp[PCH_RP(8)]" = "{
+ .flags = PCIE_RP_CLK_SRC_UNUSED,
+ }"
+ register "pcie_clk_config_flag[6]" = "PCIE_CLK_FREE_RUNNING"
# Enable PCH PCIE RP 9 using CLK 1
- register "PchPcieRpEnable[8]" = "1"
- register "PcieClkSrcClkReq[1]" = "1"
- register "PcieClkSrcUsage[1]" = "0x8"
- register "PcieRpClkReqDetect[8]" = "1"
+ register "pch_pcie_rp[PCH_RP(9)]" = "{
+ .clk_src = 1,
+ .clk_req = 1,
+ .flags = PCIE_RP_CLK_REQ_DETECT,
+ }"
# Enable PCH PCIE RP 11 for optane
- register "PchPcieRpEnable[10]" = "1"
+ register "pch_pcie_rp[PCH_RP(11)]" = "{
+ .flags = PCIE_RP_CLK_SRC_UNUSED,
+ }"
+
# Hybrid storage mode
register "HybridStorageMode" = "1"
# Enable CPU PCIE RP 1 using CLK 0
- register "CpuPcieRpEnable[0]" = "1"
- register "PcieClkSrcUsage[0]" = "0x40"
+ register "cpu_pcie_rp[CPU_RP(1)]" = "{
+ .clk_req = 0,
+ .clk_src = 0,
+ }"
# Enable CPU PCIE RP 2 using CLK 3
- register "CpuPcieRpEnable[1]" = "1"
- register "PcieClkSrcUsage[3]" = "0x41"
+ register "cpu_pcie_rp[CPU_RP(2)]" = "{
+ .clk_req = 3,
+ .clk_src = 3,
+ }"
# Enable CPU PCIE RP 3 using CLK 4
- register "CpuPcieRpEnable[2]" = "1"
- register "PcieClkSrcUsage[4]" = "0x42"
-
- # W/A to FSP issue where FSP is using PCH PCIE port
- # enable UPD to download FW on CPU PCIE
- register "PchPcieRpEnable[0]" = "1"
- register "PchPcieRpEnable[2]" = "1"
- register "PchPcieRpEnable[3]" = "1"
+ register "cpu_pcie_rp[CPU_RP(3)]" = "{
+ .clk_req = 4,
+ .clk_src = 4,
+ }"
register "SataSalpSupport" = "1"
diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h
index 0f932ce..13e77cf 100644
--- a/src/soc/intel/alderlake/chip.h
+++ b/src/soc/intel/alderlake/chip.h
@@ -19,10 +19,6 @@
#define MAX_HD_AUDIO_SNDW_LINKS 4
#define MAX_HD_AUDIO_SSP_LINKS 6
-#define PCIE_CLK_NOTUSED 0xFF
-#define PCIE_CLK_LAN 0x70
-#define PCIE_CLK_FREE 0x80
-
struct soc_intel_alderlake_config {
/* Common struct containing soc config data required by common code */
@@ -122,31 +118,9 @@
uint8_t PchHdaIDispLinkFrequency;
uint8_t PchHdaIDispCodecDisconnect;
- /* CPU PCIe Root Ports */
- uint8_t CpuPcieRpEnable[CONFIG_MAX_CPU_ROOT_PORTS];
-
- /* PCH PCIe Root Ports */
- uint8_t PchPcieRpEnable[CONFIG_MAX_PCH_ROOT_PORTS];
- uint8_t PcieRpHotPlug[CONFIG_MAX_PCH_ROOT_PORTS];
- /* PCIe output clocks type to PCIe devices.
- * 0-23: PCH rootport, 0x70: LAN, 0x80: unspecified but in use,
- * 0xFF: not used */
- uint8_t PcieClkSrcUsage[CONFIG_MAX_PCIE_CLOCK_SRC];
- /* PCIe ClkReq-to-ClkSrc mapping, number of clkreq signal assigned to
- * clksrc. */
- uint8_t PcieClkSrcClkReq[CONFIG_MAX_PCIE_CLOCK_REQ];
-
- /* Probe CLKREQ# signal before enabling CLKREQ# based power management.*/
- uint8_t PcieRpClkReqDetect[CONFIG_MAX_PCH_ROOT_PORTS];
-
- /* PCIe RP L1 substate */
- enum L1_substates_control PcieRpL1Substates[CONFIG_MAX_PCH_ROOT_PORTS];
-
- /* PCIe LTR: Enable (1) / Disable (0) */
- uint8_t PcieRpLtrEnable[CONFIG_MAX_PCH_ROOT_PORTS];
-
- /* PCIE RP Advanced Error Report: Enable (1) / Disable (0) */
- uint8_t PcieRpAdvancedErrorReporting[CONFIG_MAX_PCH_ROOT_PORTS];
+ struct pcie_rp_config pch_pcie_rp[CONFIG_MAX_PCH_ROOT_PORTS];
+ struct pcie_rp_config cpu_pcie_rp[CONFIG_MAX_CPU_ROOT_PORTS];
+ uint8_t pcie_clk_config_flag[CONFIG_MAX_PCIE_CLOCK_SRC];
/* Gfx related */
enum {
diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c
index 35f7a3c..6e6f1af 100644
--- a/src/soc/intel/alderlake/fsp_params.c
+++ b/src/soc/intel/alderlake/fsp_params.c
@@ -15,6 +15,7 @@
#include <soc/gpio_soc_defs.h>
#include <soc/intel/common/vbt.h>
#include <soc/pci_devs.h>
+#include <soc/pcie.h>
#include <soc/ramstage.h>
#include <soc/soc_chip.h>
#include <string.h>
@@ -93,6 +94,7 @@
const struct microcode *microcode_file;
size_t microcode_len;
FSP_S_CONFIG *params = &supd->FspsConfig;
+ uint32_t enable_mask;
struct device *dev;
struct soc_intel_alderlake_config *config;
@@ -270,19 +272,19 @@
/* Enable Hybrid storage auto detection */
params->HybridStorageMode = config->HybridStorageMode;
+ enable_mask = pcie_rp_enable_mask(get_pch_pcie_rp_table());
for (i = 0; i < CONFIG_MAX_PCH_ROOT_PORTS; i++) {
+ if (!(enable_mask & BIT(i)))
+ continue;
+ const struct pcie_rp_config *rp_cfg = &config->pch_pcie_rp[i];
params->PcieRpL1Substates[i] =
- get_l1_substate_control(config->PcieRpL1Substates[i]);
- params->PcieRpLtrEnable[i] = config->PcieRpLtrEnable[i];
- params->PcieRpAdvancedErrorReporting[i] =
- config->PcieRpAdvancedErrorReporting[i];
- params->PcieRpHotPlug[i] = config->PcieRpHotPlug[i];
+ get_l1_substate_control(rp_cfg->PcieRpL1Substates);
+ params->PcieRpLtrEnable[i] = !!(rp_cfg->flags & PCIE_RP_LTR);
+ params->PcieRpAdvancedErrorReporting[i] = !!(rp_cfg->flags & PCIE_RP_AER);
+ params->PcieRpHotPlug[i] = !!(rp_cfg->flags & PCIE_RP_HOTPLUG);
+ params->PcieRpClkReqDetect[i] = !!(rp_cfg->flags & PCIE_RP_CLK_REQ_DETECT);
}
- /* Enable ClkReqDetect for enabled port */
- memcpy(params->PcieRpClkReqDetect, config->PcieRpClkReqDetect,
- sizeof(config->PcieRpClkReqDetect));
-
params->PmSupport = 1;
params->Hwp = 1;
params->Cx = 1;
diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c
index 0154cb4..3852467 100644
--- a/src/soc/intel/alderlake/romstage/fsp_params.c
+++ b/src/soc/intel/alderlake/romstage/fsp_params.c
@@ -7,20 +7,58 @@
#include <fsp/util.h>
#include <intelblocks/cpulib.h>
#include <intelblocks/mp_init.h>
+#include <intelblocks/pcie_rp.h>
#include <soc/gpio_soc_defs.h>
#include <soc/iomap.h>
#include <soc/msr.h>
#include <soc/pci_devs.h>
+#include <soc/pcie.h>
#include <soc/romstage.h>
#include <soc/soc_chip.h>
#include <string.h>
+#define FSP_CLK_NOTUSED 0xFF
+#define FSP_CLK_LAN 0x70
+#define FSP_CLK_FREE_RUNNING 0x80
+
+#define CPU_PCIE_BASE 0x40
+
+enum pcie_rp_type {
+ PCH_PCIE_RP,
+ CPU_PCIE_RP,
+};
+
+static uint8_t clk_src_to_fsp(enum pcie_rp_type type, int rp_number)
+{
+ assert(type == PCH_PCIE_RP || type == CPU_PCIE_RP);
+
+ if (type == PCH_PCIE_RP)
+ return rp_number;
+ else // type == CPU_PCIE_RP
+ return CPU_PCIE_BASE + rp_number;
+}
+
+static void pcie_rp_init(FSP_M_CONFIG *m_cfg, uint32_t en_mask, enum pcie_rp_type type,
+ const struct pcie_rp_config *cfg, size_t cfg_count)
+{
+ size_t i;
+
+ for (i = 0; i < cfg_count; i++) {
+ if (!(en_mask & BIT(i)))
+ continue;
+ if (cfg[i].flags & PCIE_RP_CLK_SRC_UNUSED)
+ continue;
+ if (!(cfg[i].flags & PCIE_RP_CLK_REQ_UNUSED))
+ m_cfg->PcieClkSrcClkReq[cfg[i].clk_src] = cfg[i].clk_req;
+ m_cfg->PcieClkSrcUsage[cfg[i].clk_src] = clk_src_to_fsp(type, i);
+ }
+}
+
static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
const struct soc_intel_alderlake_config *config)
{
- unsigned int i;
- uint32_t mask = 0;
const struct device *dev;
+ unsigned int i;
dev = pcidev_path_on_root(SA_DEVFN_IGD);
if (!CONFIG(SOC_INTEL_DISABLE_IGD) && is_dev_enabled(dev))
@@ -42,18 +80,6 @@
/* Set CpuRatio to match existing MSR value */
m_cfg->CpuRatio = (rdmsr(MSR_FLEX_RATIO).lo >> 8) & 0xff;
- for (i = 0; i < ARRAY_SIZE(config->PchPcieRpEnable); i++) {
- if (config->PchPcieRpEnable[i])
- mask |= (1 << i);
- }
- m_cfg->PcieRpEnableMask = mask;
-
- memcpy(m_cfg->PcieClkSrcUsage, config->PcieClkSrcUsage,
- sizeof(config->PcieClkSrcUsage));
-
- memcpy(m_cfg->PcieClkSrcClkReq, config->PcieClkSrcClkReq,
- sizeof(config->PcieClkSrcClkReq));
-
m_cfg->PrmrrSize = get_valid_prmrr_size();
m_cfg->EnableC6Dram = config->enable_c6dram;
/* Disable BIOS Guard */
@@ -116,6 +142,27 @@
m_cfg->PchHdaIDispLinkFrequency = config->PchHdaIDispLinkFrequency;
m_cfg->PchHdaIDispCodecDisconnect = config->PchHdaIDispCodecDisconnect;
+ /* Disable all PCIe clock sources by default. And set RP irrelevant clock. */
+ for (i = 0; i < CONFIG_MAX_PCIE_CLOCK_SRC; i++) {
+ if (config->pcie_clk_config_flag[i] & PCIE_CLK_FREE_RUNNING)
+ m_cfg->PcieClkSrcUsage[i] = FSP_CLK_FREE_RUNNING;
+ else if (config->pcie_clk_config_flag[i] & PCIE_CLK_LAN)
+ m_cfg->PcieClkSrcUsage[i] = FSP_CLK_LAN;
+ else
+ m_cfg->PcieClkSrcUsage[i] = FSP_CLK_NOTUSED;
+ m_cfg->PcieClkSrcClkReq[i] = FSP_CLK_NOTUSED;
+ }
+
+ /* PCIE ports */
+ m_cfg->PcieRpEnableMask = pcie_rp_enable_mask(get_pch_pcie_rp_table());
+ pcie_rp_init(m_cfg, m_cfg->PcieRpEnableMask, PCH_PCIE_RP, config->pch_pcie_rp,
+ CONFIG_MAX_PCH_ROOT_PORTS);
+
+ /* CPU PCIE ports */
+ m_cfg->CpuPcieRpEnableMask = pcie_rp_enable_mask(get_cpu_pcie_rp_table());
+ pcie_rp_init(m_cfg, m_cfg->CpuPcieRpEnableMask, CPU_PCIE_RP, config->cpu_pcie_rp,
+ CONFIG_MAX_CPU_ROOT_PORTS);
+
/* ISH */
dev = pcidev_path_on_root(PCH_DEVFN_ISH);
m_cfg->PchIshEnable = is_dev_enabled(dev);
@@ -156,13 +203,6 @@
/* Skip CPU replacement check */
m_cfg->SkipCpuReplacementCheck = !config->CpuReplacementCheck;
- mask = 0;
- for (i = 0; i < ARRAY_SIZE(config->CpuPcieRpEnable); i++) {
- if (config->CpuPcieRpEnable[i])
- mask |= (1 << i);
- }
- m_cfg->CpuPcieRpEnableMask = mask;
-
m_cfg->TmeEnable = CONFIG(INTEL_TME);
/* Skip GPIO configuration from FSP */
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