CK HU would like Duan huayang to review this change.
soc/mediatek/mt8192: Do dramc analog init setting
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Change-Id: I53b30a2bbed5acb363f85f7cbc7f255fdbc52304
---
M src/soc/mediatek/mt8192/Makefile.inc
A src/soc/mediatek/mt8192/dramc_ana_init_config.c
M src/soc/mediatek/mt8192/dramc_pi_basic_api.c
A src/soc/mediatek/mt8192/dramc_subsys_config.c
M src/soc/mediatek/mt8192/emi.c
5 files changed, 1,411 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/44727/1
diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc
index bfa3316..e3463cd 100644
--- a/src/soc/mediatek/mt8192/Makefile.inc
+++ b/src/soc/mediatek/mt8192/Makefile.inc
@@ -17,6 +17,7 @@
romstage-y += ../common/cbmem.c
romstage-y += dramc_pi_main.c dramc_pi_basic_api.c dramc_pi_calibration_api.c dramc_utility.c dramc_dvfs.c dramc_tracking.c
+romstage-y += dramc_subsys_config.c dramc_ana_init_config.c
romstage-y += emi.c
romstage-y += flash_controller.c
romstage-y += ../common/gpio.c gpio.c
diff --git a/src/soc/mediatek/mt8192/dramc_ana_init_config.c b/src/soc/mediatek/mt8192/dramc_ana_init_config.c
new file mode 100644
index 0000000..0fd3a9a
--- /dev/null
+++ b/src/soc/mediatek/mt8192/dramc_ana_init_config.c
@@ -0,0 +1,1242 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/dramc_pi_api.h>
+#include <soc/dramc_register.h>
+
+static void suspend_on(void)
+{
+ SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_lp_ctrl0,
+ B0_LP_CTRL0_RG_ARDMSUS_10_B0, 0);
+ SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_lp_ctrl0,
+ B1_LP_CTRL0_RG_ARDMSUS_10_B1, 0);
+ dramc_set_broadcast(DRAMC_BROADCAST_OFF);
+ for (u8 chn = 0; chn < CHANNEL_MAX; chn++)
+ SET32_BITFIELDS(&ch[chn].phy_ao.ca_lp_ctrl0,
+ CA_LP_CTRL0_RG_ARDMSUS_10_CA, 0);
+ dramc_set_broadcast(DRAMC_BROADCAST_ON);
+}
+
+void resetb_pull_dn(void)
+{
+ SET32_BITFIELDS(&ch[0].phy_ao.ca_cmd11,
+ CA_CMD11_RG_RRESETB_DRVP, 1,
+ CA_CMD11_RG_RRESETB_DRVN, 1,
+ CA_CMD11_RG_TX_RRESETB_DDR3_SEL, 1,
+ CA_CMD11_RG_TX_RRESETB_PULL_DN, 1);
+ SET32_BITFIELDS(&ch[0].phy_ao.misc_ctrl1,
+ MISC_CTRL1_R_DMRRESETB_I_OPT, 1);
+ SET32_BITFIELDS(&ch[0].phy_ao.misc_ctrl1,
+ MISC_CTRL1_R_DMDA_RRESETB_E, 1);
+ SET32_BITFIELDS(&ch[0].phy_ao.ca_cmd11,
+ CA_CMD11_RG_TX_RRESETB_PULL_DN, 0);
+}
+
+static void spm_control(ana_top_config *a_cfg)
+{
+ u8 new_8x_mode = a_cfg->new_8x_mode;
+
+ SET32_BITFIELDS(&ch[0].phy_ao.misc_lp_ctrl,
+ MISC_LP_CTRL_RG_ARDMSUS_10_LP_SEL, 1,
+ MISC_LP_CTRL_RG_RIMP_DMSUS_10_LP_SEL, 1,
+ MISC_LP_CTRL_RG_RRESETB_LP_SEL, 1,
+ MISC_LP_CTRL_RG_RPHYPLL_RESETB_LP_SEL, 1,
+ MISC_LP_CTRL_RG_RPHYPLL_EN_LP_SEL, 1,
+ MISC_LP_CTRL_RG_RCLRPLL_EN_LP_SEL, 1,
+ MISC_LP_CTRL_RG_RPHYPLL_ADA_MCK8X_EN_LP_SEL, 1,
+ MISC_LP_CTRL_RG_RPHYPLL_AD_MCK8X_EN_LP_SEL, 1,
+ MISC_LP_CTRL_RG_RPHYPLL_TOP_REV_0_LP_SEL, 1,
+ MISC_LP_CTRL_RG_SC_ARPI_RESETB_8X_SEQ_LP_SEL, new_8x_mode,
+ MISC_LP_CTRL_RG_ADA_MCK8X_8X_SEQ_LP_SEL, new_8x_mode,
+ MISC_LP_CTRL_RG_AD_MCK8X_8X_SEQ_LP_SEL, new_8x_mode,
+ MISC_LP_CTRL_RG_MIDPI_EN_8X_SEQ_LP_SEL, new_8x_mode,
+ MISC_LP_CTRL_RG_MIDPI_CKDIV4_EN_8X_SEQ_LP_SEL, new_8x_mode,
+ MISC_LP_CTRL_RG_MCK8X_CG_SRC_LP_SEL, new_8x_mode,
+ MISC_LP_CTRL_RG_MCK8X_CG_SRC_AND_LP_SEL, new_8x_mode);
+ SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_lp_ctrl0,
+ B0_LP_CTRL0_RG_ARDMSUS_10_B0_LP_SEL, 1,
+ B0_LP_CTRL0_RG_ARDQ_RESETB_B0_LP_SEL, 1,
+ B0_LP_CTRL0_RG_ARPI_RESETB_B0_LP_SEL, 1,
+ B0_LP_CTRL0_RG_B0_MS_SLV_LP_SEL, 0,
+ B0_LP_CTRL0_RG_ARDLL_PHDET_EN_B0_LP_SEL, 1,
+ B0_LP_CTRL0_RG_RX_ARDQ_BIAS_EN_B0_LP_SEL, 0,
+ B0_LP_CTRL0_DA_ARPI_CG_MCK_B0_LP_SEL, 1,
+ B0_LP_CTRL0_DA_ARPI_CG_MCK_FB2DLL_B0_LP_SEL, 1,
+ B0_LP_CTRL0_DA_ARPI_CG_MCTL_B0_LP_SEL, 1,
+ B0_LP_CTRL0_DA_ARPI_CG_FB_B0_LP_SEL, 1,
+ B0_LP_CTRL0_DA_ARPI_CG_DQ_B0_LP_SEL, 1);
+ SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_lp_ctrl0,
+ B0_LP_CTRL0_DA_ARPI_CG_DQM_B0_LP_SEL, 1,
+ B0_LP_CTRL0_DA_ARPI_CG_DQS_B0_LP_SEL, 1,
+ B0_LP_CTRL0_DA_ARPI_CG_DQSIEN_B0_LP_SEL, 1,
+ B0_LP_CTRL0_DA_ARPI_MPDIV_CG_B0_LP_SEL, 1,
+ B0_LP_CTRL0_RG_RX_ARDQ_VREF_EN_B0_LP_SEL, 1,
+ B0_LP_CTRL0_DA_ARPI_MIDPI_EN_B0_LP_SEL, 1,
+ B0_LP_CTRL0_DA_ARPI_MIDPI_CKDIV4_EN_B0_LP_SEL, 1);
+ SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_lp_ctrl0,
+ B1_LP_CTRL0_RG_ARDMSUS_10_B1_LP_SEL, 1,
+ B1_LP_CTRL0_RG_ARDQ_RESETB_B1_LP_SEL, 1,
+ B1_LP_CTRL0_RG_ARPI_RESETB_B1_LP_SEL, 1,
+ B1_LP_CTRL0_RG_B1_MS_SLV_LP_SEL, 0,
+ B1_LP_CTRL0_RG_ARDLL_PHDET_EN_B1_LP_SEL, 1,
+ B1_LP_CTRL0_RG_RX_ARDQ_BIAS_EN_B1_LP_SEL, 0,
+ B1_LP_CTRL0_DA_ARPI_CG_MCK_B1_LP_SEL, 1,
+ B1_LP_CTRL0_DA_ARPI_CG_MCK_FB2DLL_B1_LP_SEL, 1,
+ B1_LP_CTRL0_DA_ARPI_CG_MCTL_B1_LP_SEL, 1,
+ B1_LP_CTRL0_DA_ARPI_CG_FB_B1_LP_SEL, 1,
+ B1_LP_CTRL0_DA_ARPI_CG_DQ_B1_LP_SEL, 1);
+ SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_lp_ctrl0,
+ B1_LP_CTRL0_DA_ARPI_CG_DQM_B1_LP_SEL, 1,
+ B1_LP_CTRL0_DA_ARPI_CG_DQS_B1_LP_SEL, 1,
+ B1_LP_CTRL0_DA_ARPI_CG_DQSIEN_B1_LP_SEL, 1,
+ B1_LP_CTRL0_DA_ARPI_MPDIV_CG_B1_LP_SEL, 1,
+ B1_LP_CTRL0_RG_RX_ARDQ_VREF_EN_B1_LP_SEL, 1,
+ B1_LP_CTRL0_DA_ARPI_MIDPI_EN_B1_LP_SEL, 1,
+ B1_LP_CTRL0_DA_ARPI_MIDPI_CKDIV4_EN_B1_LP_SEL, 1);
+
+ dramc_set_broadcast(DRAMC_BROADCAST_OFF);
+ for (u8 chn = 0; chn < CHANNEL_MAX; chn++) {
+ SET32_BITFIELDS(&ch[chn].phy_ao.ca_lp_ctrl0,
+ CA_LP_CTRL0_RG_ARDMSUS_10_CA_LP_SEL, 1,
+ CA_LP_CTRL0_RG_ARCMD_RESETB_LP_SEL, 1,
+ CA_LP_CTRL0_RG_ARPI_RESETB_CA_LP_SEL, 1,
+ CA_LP_CTRL0_RG_ARDLL_PHDET_EN_CA_LP_SEL, 1,
+ CA_LP_CTRL0_RG_TX_ARCS_PULL_UP_LP_SEL, 1,
+ CA_LP_CTRL0_RG_TX_ARCS_PULL_DN_LP_SEL, 1,
+ CA_LP_CTRL0_RG_TX_ARCA_PULL_UP_LP_SEL, 1,
+ CA_LP_CTRL0_RG_TX_ARCA_PULL_DN_LP_SEL, 1,
+ CA_LP_CTRL0_DA_ARPI_CG_MCK_CA_LP_SEL, 1,
+ CA_LP_CTRL0_DA_ARPI_CG_MCK_FB2DLL_CA_LP_SEL, 1,
+ CA_LP_CTRL0_DA_ARPI_CG_MCTL_CA_LP_SEL, 1,
+ CA_LP_CTRL0_DA_ARPI_CG_FB_CA_LP_SEL, 1);
+ SET32_BITFIELDS(&ch[chn].phy_ao.ca_lp_ctrl0,
+ CA_LP_CTRL0_DA_ARPI_CG_CS_LP_SEL, 1,
+ CA_LP_CTRL0_DA_ARPI_CG_CLK_LP_SEL, 1,
+ CA_LP_CTRL0_DA_ARPI_CG_CMD_LP_SEL, 1,
+ CA_LP_CTRL0_DA_ARPI_CG_CLKIEN_LP_SEL, 1,
+ CA_LP_CTRL0_DA_ARPI_MPDIV_CG_CA_LP_SEL, 1,
+ CA_LP_CTRL0_RG_RX_ARCMD_VREF_EN_LP_SEL, 1,
+ CA_LP_CTRL0_DA_ARPI_MIDPI_EN_CA_LP_SEL, 1,
+ CA_LP_CTRL0_DA_ARPI_MIDPI_CKDIV4_EN_CA_LP_SEL, 1,
+ CA_LP_CTRL0_RG_RX_ARCMD_BIAS_EN_LP_SEL, 0);
+ }
+
+ if (a_cfg->dll_async_en == 1) {
+ for (u8 chn = 0; chn < CHANNEL_MAX; chn++)
+ SET32_BITFIELDS(&ch[chn].phy_ao.ca_lp_ctrl0,
+ CA_LP_CTRL0_RG_CA_MS_SLV_LP_SEL, a_cfg->all_slave_en==0);
+ } else {
+ SET32_BITFIELDS(&ch[0].phy_ao.ca_lp_ctrl0,
+ CA_LP_CTRL0_RG_CA_MS_SLV_LP_SEL, a_cfg->all_slave_en==0);
+ SET32_BITFIELDS(&ch[1].phy_ao.ca_lp_ctrl0,
+ CA_LP_CTRL0_RG_CA_MS_SLV_LP_SEL, 0);
+ }
+ dramc_set_broadcast(DRAMC_BROADCAST_ON);
+
+ SET32_BITFIELDS(&ch[0].phy_ao.misc_cg_ctrl9,
+ MISC_CG_CTRL9_RG_M_CK_OPENLOOP_MODE_EN, 1,
+ MISC_CG_CTRL9_RG_MCK4X_I_OPENLOOP_MODE_EN, 1,
+ MISC_CG_CTRL9_RG_CG_DDR400_MCK4X_I_OFF, 1,
+ MISC_CG_CTRL9_RG_DDR400_MCK4X_I_FORCE_ON, 0,
+ MISC_CG_CTRL9_RG_MCK4X_I_FB_CK_CG_OFF, 1,
+ MISC_CG_CTRL9_RG_MCK4X_Q_OPENLOOP_MODE_EN, 1,
+ MISC_CG_CTRL9_RG_CG_DDR400_MCK4X_Q_OFF, 1,
+ MISC_CG_CTRL9_RG_DDR400_MCK4X_Q_FORCE_ON, 0,
+ MISC_CG_CTRL9_RG_MCK4X_Q_FB_CK_CG_OFF, 1);
+}
+
+static void ana_tx_nonshuffle_config(ana_top_config *a_cfg)
+{
+ SET32_BITFIELDS(&ch[0].phy_ao.ca_cmd6,
+ CA_CMD6_RG_TX_ARCMD_DDR3_SEL, 0,
+ CA_CMD6_RG_TX_ARCMD_DDR4_SEL, 0,
+ CA_CMD6_RG_TX_ARCMD_LP4_SEL, 1);
+ SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq6,
+ B0_DQ6_RG_TX_ARDQ_DDR3_SEL_B0, 0,
+ B0_DQ6_RG_TX_ARDQ_DDR4_SEL_B0, !(a_cfg->aphy_comb_en),
+ B0_DQ6_RG_TX_ARDQ_LP4_SEL_B0, a_cfg->aphy_comb_en);
+ SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq6,
+ B1_DQ6_RG_TX_ARDQ_DDR3_SEL_B1, 0,
+ B1_DQ6_RG_TX_ARDQ_DDR4_SEL_B1, !(a_cfg->aphy_comb_en),
+ B1_DQ6_RG_TX_ARDQ_LP4_SEL_B1, a_cfg->aphy_comb_en);
+ dramc_dbg("[CONFIGURE PHASE]: ANA_TX\n");
+ SET32_BITFIELDS(&ch[0].phy_ao.ca_cmd2,
+ CA_CMD2_RG_TX_ARCMD_OE_DIS_CA, 1,
+ CA_CMD2_RG_TX_ARCMD_ODTEN_DIS_CA, 0,
+ CA_CMD2_RG_TX_ARCLK_OE_DIS_CA, 0,
+ CA_CMD2_RG_TX_ARCLK_ODTEN_DIS_CA, 0,
+ CA_CMD2_RG_TX_ARCS_OE_TIE_SEL_CA, 1,
+ CA_CMD2_RG_TX_ARCS_OE_TIE_EN_CA, 1,
+ CA_CMD2_RG_TX_ARCA_OE_TIE_SEL_CA, 0,
+ CA_CMD2_RG_TX_ARCA_OE_TIE_EN_CA, 0xff);
+ SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq2,
+ B0_DQ2_RG_TX_ARDQ_OE_DIS_B0, 0,
+ B0_DQ2_RG_TX_ARDQ_ODTEN_DIS_B0, 0,
+ B0_DQ2_RG_TX_ARDQM0_OE_DIS_B0, 0,
+ B0_DQ2_RG_TX_ARDQM0_ODTEN_DIS_B0, 0,
+ B0_DQ2_RG_TX_ARDQS0_OE_DIS_B0, 0,
+ B0_DQ2_RG_TX_ARDQS0_ODTEN_DIS_B0, 0);
+ SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq2,
+ B1_DQ2_RG_TX_ARDQ_OE_DIS_B1, 0,
+ B1_DQ2_RG_TX_ARDQ_ODTEN_DIS_B1, 0,
+ B1_DQ2_RG_TX_ARDQM0_OE_DIS_B1, 0,
+ B1_DQ2_RG_TX_ARDQM0_ODTEN_DIS_B1, 0,
+ B1_DQ2_RG_TX_ARDQS0_OE_DIS_B1, 0,
+ B1_DQ2_RG_TX_ARDQS0_ODTEN_DIS_B1, 0);
+ SET32_BITFIELDS(&ch[0].phy_ao.ca_cmd3,
+ CA_CMD3_RG_TX_ARCMD_EN, 1,
+ CA_CMD3_RG_ARCMD_RESETB, 1);
+ SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq3,
+ B0_DQ3_RG_ARDQ_RESETB_B0, 1,
+ B0_DQ3_RG_TX_ARDQ_EN_B0, 1);
+ SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq3,
+ B1_DQ3_RG_ARDQ_RESETB_B1, 1,
+ B1_DQ3_RG_TX_ARDQ_EN_B1, 1);
+}
+
+static void ana_rx_nonshuffle_config(void)
+{
+ SET32_BITFIELDS(&ch[0].phy_ao.ca_cmd6,
+ CA_CMD6_RG_RX_ARCMD_DDR3_SEL, 0,
+ CA_CMD6_RG_RX_ARCMD_DDR4_SEL, 0,
+ CA_CMD6_RG_RX_ARCMD_BIAS_VREF_SEL, 0,
+ CA_CMD6_RG_RX_ARCMD_RES_BIAS_EN, 0);
+ SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq5,
+ B0_DQ5_RG_RX_ARDQ_VREF_EN_B0, 1);
+ SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq6,
+ B0_DQ6_RG_RX_ARDQ_DDR3_SEL_B0, 0,
+ B0_DQ6_RG_RX_ARDQ_DDR4_SEL_B0, 1,
+ B0_DQ6_RG_RX_ARDQ_BIAS_VREF_SEL_B0, 0,
+ B0_DQ6_RG_RX_ARDQ_BIAS_EN_B0, 1,
+ B0_DQ6_RG_RX_ARDQ_OP_BIAS_SW_EN_B0, 0,
+ B0_DQ6_RG_RX_ARDQ_RES_BIAS_EN_B0, 1);
+ SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq3,
+ B0_DQ3_RG_RX_ARDQ_STBENCMP_EN_B0, 1,
+ B0_DQ3_RG_RX_ARDQ_SMT_EN_B0, 1);
+ SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq5,
+ B1_DQ5_RG_RX_ARDQ_VREF_EN_B1, 1);
+ SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq6,
+ B1_DQ6_RG_RX_ARDQ_DDR3_SEL_B1, 0,
+ B1_DQ6_RG_RX_ARDQ_DDR4_SEL_B1, 1,
+ B1_DQ6_RG_RX_ARDQ_BIAS_VREF_SEL_B1, 0,
+ B1_DQ6_RG_RX_ARDQ_BIAS_EN_B1, 1,
+ B1_DQ6_RG_RX_ARDQ_OP_BIAS_SW_EN_B1, 0,
+ B1_DQ6_RG_RX_ARDQ_RES_BIAS_EN_B1, 1);
+ SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq3,
+ B1_DQ3_RG_RX_ARDQ_STBENCMP_EN_B1, 1,
+ B1_DQ3_RG_RX_ARDQ_SMT_EN_B1, 1);
+ SET32_BITFIELDS(&ch[0].phy_ao.ca_cmd9,
+ CA_CMD9_RG_RX_ARCMD_STBEN_RESETB, 1,
+ CA_CMD9_RG_RX_ARCLK_STBEN_RESETB, 1);
+ SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq9,
+ B0_DQ9_RG_RX_ARDQ_STBEN_RESETB_B0, 1,
+ B0_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B0, 1);
+ SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq9,
+ B1_DQ9_RG_RX_ARDQ_STBEN_RESETB_B1, 1,
+ B1_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B1, 1);
+ SET32_BITFIELDS(&ch[0].phy_ao.ca_cmd8,
+ CA_CMD8_RG_RX_ARCLK_SER_RST_MODE, 1);
+ SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq8,
+ B0_DQ8_RG_RX_ARDQS_SER_RST_MODE_B0, 1);
+ SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq8,
+ B1_DQ8_RG_RX_ARDQS_SER_RST_MODE_B1, 1);
+}
+
+static void dig_dcm_nonshuffle_config(void)
+{
+ SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_rx_cg_ctrl,
+ MISC_SHU_RX_CG_CTRL_RX_DCM_EXT_DLY, 3);
+}
+
+static void ana_imp_configure(void)
+{
+ SET32_BITFIELDS(&ch[0].phy_ao.misc_imp_ctrl1,
+ MISC_IMP_CTRL1_RG_RIMP_DDR3_SEL, 0);
+ SET32_BITFIELDS(&ch[0].phy_ao.misc_imp_ctrl1,
+ MISC_IMP_CTRL1_RG_RIMP_DDR4_SEL, 1);
+ SET32_BITFIELDS(&ch[0].phy_ao.misc_imp_ctrl1,
+ MISC_IMP_CTRL1_RG_RIMP_BIAS_EN, 0,
+ MISC_IMP_CTRL1_RG_RIMP_ODT_EN, 0,
+ MISC_IMP_CTRL1_RG_RIMP_PRE_EN, 0,
+ MISC_IMP_CTRL1_RG_RIMP_VREF_EN, 0);
+}
+
+static void ana_dll_non_shuffle_config(dram_freq_grp freq_group,
+ ana_top_config *a_cfg)
+{
+ u8 pd_zone = (freq_group >= DDRFREQ_2133) ? 0x2 : 0x3;
+
+ if (a_cfg->dll_idle_mode == 1) {
+ dramc_set_broadcast(DRAMC_BROADCAST_OFF);
+ if (a_cfg->dll_async_en == 1) {
+ for (u8 chn = 0; chn < CHANNEL_MAX; chn++) {
+ SET32_BITFIELDS(&ch[chn].phy_ao.ca_dll_arpi5,
+ CA_DLL_ARPI5_RG_ARDLL_IDLE_EN_CA, 0,
+ CA_DLL_ARPI5_RG_ARDLL_PD_ZONE_CA, pd_zone);
+ SET32_BITFIELDS(&ch[chn].phy_ao.dvs_b[0].b0_dll_arpi5,
+ B0_DLL_ARPI5_RG_ARDLL_IDLE_EN_B0, 1,
+ B0_DLL_ARPI5_RG_ARDLL_PD_ZONE_B0, pd_zone);
+ SET32_BITFIELDS(&ch[chn].phy_ao.dvs_b[1].b0_dll_arpi5,
+ B1_DLL_ARPI5_RG_ARDLL_IDLE_EN_B1, 1,
+ B1_DLL_ARPI5_RG_ARDLL_PD_ZONE_B1, pd_zone);
+ }
+ } else {
+ SET32_BITFIELDS(&ch[0].phy_ao.ca_dll_arpi5,
+ CA_DLL_ARPI5_RG_ARDLL_IDLE_EN_CA, 0,
+ CA_DLL_ARPI5_RG_ARDLL_PD_ZONE_CA, pd_zone);
+ SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dll_arpi5,
+ B0_DLL_ARPI5_RG_ARDLL_IDLE_EN_B0, 1,
+ B0_DLL_ARPI5_RG_ARDLL_PD_ZONE_B0, pd_zone);
+ SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dll_arpi5,
+ B1_DLL_ARPI5_RG_ARDLL_IDLE_EN_B1, 1,
+ B1_DLL_ARPI5_RG_ARDLL_PD_ZONE_B1, pd_zone);
+ SET32_BITFIELDS(&ch[1].phy_ao.ca_dll_arpi5,
+ CA_DLL_ARPI5_RG_ARDLL_IDLE_EN_CA, 1,
+ CA_DLL_ARPI5_RG_ARDLL_PD_ZONE_CA, pd_zone);
+ SET32_BITFIELDS(&ch[1].phy_ao.dvs_b[0].b0_dll_arpi5,
+ B0_DLL_ARPI5_RG_ARDLL_IDLE_EN_B0, 1,
+ B0_DLL_ARPI5_RG_ARDLL_PD_ZONE_B0, pd_zone);
+ SET32_BITFIELDS(&ch[1].phy_ao.dvs_b[1].b0_dll_arpi5,
+ B1_DLL_ARPI5_RG_ARDLL_IDLE_EN_B1, 1,
+ B1_DLL_ARPI5_RG_ARDLL_PD_ZONE_B1, pd_zone);
+ }
+ dramc_set_broadcast(DRAMC_BROADCAST_ON);
+ }
+
+ SET32_BITFIELDS(&ch[0].phy_ao.ca_dll_arpi1,
+ CA_DLL_ARPI1_RG_ARPI_CLKIEN_JUMP_EN, 0,
+ CA_DLL_ARPI1_RG_ARPI_CMD_JUMP_EN, 0,
+ CA_DLL_ARPI1_RG_ARPI_CLK_JUMP_EN, 0,
+ CA_DLL_ARPI1_RG_ARPI_CS_JUMP_EN, 0,
+ CA_DLL_ARPI1_RG_ARPI_FB_JUMP_EN_CA, 0,
+ CA_DLL_ARPI1_RG_ARPI_MCTL_JUMP_EN_CA, 0,
+ CA_DLL_ARPI1_RG_ARPISM_MCK_SEL_CA, 1,
+ CA_DLL_ARPI1_RG_ARPISM_MCK_SEL_CA_REG_OPT, 0);
+ SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dll_arpi1,
+ B0_DLL_ARPI1_RG_ARPI_DQSIEN_JUMP_EN_B0, 0,
+ B0_DLL_ARPI1_RG_ARPI_DQ_JUMP_EN_B0, 0,
+ B0_DLL_ARPI1_RG_ARPI_DQM_JUMP_EN_B0, 0,
+ B0_DLL_ARPI1_RG_ARPI_DQS_JUMP_EN_B0, 0,
+ B0_DLL_ARPI1_RG_ARPI_FB_JUMP_EN_B0, 0,
+ B0_DLL_ARPI1_RG_ARPI_MCTL_JUMP_EN_B0, 0,
+ B0_DLL_ARPI1_RG_ARPISM_MCK_SEL_B0, 0,
+ B0_DLL_ARPI1_RG_ARPISM_MCK_SEL_B0_REG_OPT, 0);
+ SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dll_arpi1,
+ B1_DLL_ARPI1_RG_ARPI_DQSIEN_JUMP_EN_B1, 0,
+ B1_DLL_ARPI1_RG_ARPI_DQ_JUMP_EN_B1, 0,
+ B1_DLL_ARPI1_RG_ARPI_DQM_JUMP_EN_B1, 0,
+ B1_DLL_ARPI1_RG_ARPI_DQS_JUMP_EN_B1, 0,
+ B1_DLL_ARPI1_RG_ARPI_FB_JUMP_EN_B1, 0,
+ B1_DLL_ARPI1_RG_ARPI_MCTL_JUMP_EN_B1, 0,
+ B1_DLL_ARPI1_RG_ARPISM_MCK_SEL_B1, 0,
+ B1_DLL_ARPI1_RG_ARPISM_MCK_SEL_B1_REG_OPT, 0);
+
+ dramc_set_broadcast(DRAMC_BROADCAST_OFF);
+ for (u8 chn = 0; chn < CHANNEL_MAX; chn++) {
+ SET32_BITFIELDS(&ch[chn].phy_ao.ca_dll_arpi5,
+ CA_DLL_ARPI5_RG_ARDLL_FJ_OUT_MODE_CA, 0,
+ CA_DLL_ARPI5_RG_ARDLL_FJ_OUT_MODE_SEL_CA, 0,
+ CA_DLL_ARPI5_RG_ARDLL_DIV_DEC_CA, 0,
+ CA_DLL_ARPI5_RG_ARDLL_MON_SEL_CA, 0);
+ SET32_BITFIELDS(&ch[chn].phy_ao.dvs_b[0].b0_dll_arpi5,
+ B0_DLL_ARPI5_RG_ARDLL_FJ_OUT_MODE_B0, 0,
+ B0_DLL_ARPI5_RG_ARDLL_FJ_OUT_MODE_SEL_B0, 0,
+ B0_DLL_ARPI5_RG_ARDLL_DIV_DEC_B0, 0,
+ B0_DLL_ARPI5_RG_ARDLL_MON_SEL_B0, 0);
+ SET32_BITFIELDS(&ch[chn].phy_ao.dvs_b[1].b0_dll_arpi5,
+ B1_DLL_ARPI5_RG_ARDLL_FJ_OUT_MODE_B1, 0,
+ B1_DLL_ARPI5_RG_ARDLL_FJ_OUT_MODE_SEL_B1, 0,
+ B1_DLL_ARPI5_RG_ARDLL_DIV_DEC_B1, 0,
+ B1_DLL_ARPI5_RG_ARDLL_MON_SEL_B1, 0);
+ }
+ dramc_set_broadcast(DRAMC_BROADCAST_ON);
+}
+
+static void ana_pll_shuffle_Config(ana_dvfs_core *dvfs_core)
+{
+ u8 prediv = 1;
+ u8 posdiv = 0;
+ u8 fbk_sel = 0;
+ u8 div16_ck_sel = 0;
+ u32 pcw;
+ u32 pll_freq = dvfs_core->pll_freq;
+ u32 xtal_freq = 26;
+
+ if (dvfs_core->dq_ca_open == 1)
+ div16_ck_sel = 1;
+ else
+ fbk_sel = (pll_freq > 3800) ? 1 : 0;
+
+ pcw = (pll_freq/xtal_freq) << (8 + 1 -fbk_sel-prediv - posdiv);
+ dramc_dbg("pll_freq:%d, fbk_sel:%d, pcw = %#x\n", pll_freq, fbk_sel, pcw);
+
+ SET32_BITFIELDS(&ch[0].phy_ao.phypll1,
+ PHYPLL1_RG_RPHYPLL_TST_EN, 0,
+ PHYPLL1_RG_RPHYPLL_TSTOP_EN, 0);
+ SET32_BITFIELDS(&ch[0].phy_ao.shu_phypll0,
+ SHU_PHYPLL0_RG_RPHYPLL_RESERVED, 0,
+ SHU_PHYPLL0_RG_RPHYPLL_ICHP, 0);
+ SET32_BITFIELDS(&ch[0].phy_ao.shu_clrpll0,
+ SHU_CLRPLL0_RG_RCLRPLL_RESERVED, 0,
+ SHU_CLRPLL0_RG_RCLRPLL_ICHP, 0);
+ SET32_BITFIELDS(&ch[0].phy_ao.shu_phypll2,
+ SHU_PHYPLL2_RG_RPHYPLL_PREDIV, prediv,
+ SHU_PHYPLL2_RG_RPHYPLL_POSDIV, posdiv);
+ SET32_BITFIELDS(&ch[0].phy_ao.shu_clrpll2,
+ SHU_CLRPLL2_RG_RCLRPLL_PREDIV, prediv,
+ SHU_CLRPLL2_RG_RCLRPLL_POSDIV, posdiv);
+ SET32_BITFIELDS(&ch[0].phy_ao.shu_phypll1,
+ SHU_PHYPLL1_RG_RPHYPLL_SDM_PCW, pcw,
+ SHU_PHYPLL1_RG_RPHYPLL_SDM_PCW_CHG, 1,
+ SHU_PHYPLL1_RG_RPHYPLL_SDM_FRA_EN, 0);
+ SET32_BITFIELDS(&ch[0].phy_ao.shu_clrpll1,
+ SHU_CLRPLL1_RG_RCLRPLL_SDM_PCW, pcw,
+ SHU_CLRPLL1_RG_RCLRPLL_SDM_PCW_CHG, 1,
+ SHU_CLRPLL1_RG_RCLRPLL_SDM_FRA_EN, 0);
+ SET32_BITFIELDS(&ch[0].phy_ao.shu_pll1,
+ SHU_PLL1_RG_RPHYPLLGP_CK_SEL, 1,
+ SHU_PLL1_R_SHU_AUTO_PLL_MUX, 1);
+ SET32_BITFIELDS(&ch[0].phy_ao.shu_phypll3,
+ SHU_PHYPLL3_RG_RPHYPLL_LVROD_EN, 0,
+ SHU_PHYPLL3_RG_RPHYPLL_RST_DLY, 1,
+ SHU_PHYPLL3_RG_RPHYPLL_FBKSEL, fbk_sel);
+ SET32_BITFIELDS(&ch[0].phy_ao.shu_clrpll3,
+ SHU_CLRPLL3_RG_RCLRPLL_LVROD_EN, 0,
+ SHU_CLRPLL3_RG_RCLRPLL_RST_DLY, 1,
+ SHU_CLRPLL3_RG_RCLRPLL_FBKSEL, fbk_sel);
+ if (dvfs_core->dq_ca_open == 1) {
+ SET32_BITFIELDS(&ch[0].phy_ao.shu_misc_clk_ctrl0,
+ SHU_MISC_CLK_CTRL0_M_CK_OPENLOOP_MODE_SEL,
+ dvfs_core->dq_ca_open);
+ SET32_BITFIELDS(&ch[0].phy_ao.shu_phypll3,
+ SHU_PHYPLL3_RG_RPHYPLL_MONCK_EN, 1,
+ SHU_PHYPLL3_RG_RPHYPLL_DIV_CK_SEL, div16_ck_sel);
+ SET32_BITFIELDS(&ch[0].phy_ao.shu_clrpll3,
+ SHU_CLRPLL3_RG_RCLRPLL_MONCK_EN, 1,
+ SHU_CLRPLL3_RG_RCLRPLL_DIV_CK_SEL, div16_ck_sel);
+ }
+ dramc_dbg("PLL\n");
+}
+
+static void ana_arpi_shuffle_config(ana_top_config *a_cfg, ana_dvfs_core *tr)
+{
+ SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_dll_arpi3,
+ SHU_CA_DLL_ARPI3_RG_ARPI_CLKIEN_EN, 0,
+ SHU_CA_DLL_ARPI3_RG_ARPI_CMD_EN, !(tr->dq_semi_open),
+ SHU_CA_DLL_ARPI3_RG_ARPI_CS_EN, !(tr->dq_semi_open));
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dll_arpi3,
+ SHU_B0_DLL_ARPI3_RG_ARPI_DQSIEN_EN_B0, !(tr->dq_semi_open),
+ SHU_B0_DLL_ARPI3_RG_ARPI_DQ_EN_B0, !(tr->dq_semi_open),
+ SHU_B0_DLL_ARPI3_RG_ARPI_DQM_EN_B0, !(tr->dq_semi_open),
+ SHU_B0_DLL_ARPI3_RG_ARPI_DQS_EN_B0, !(tr->dq_semi_open),
+ SHU_B0_DLL_ARPI3_RG_ARPI_FB_EN_B0, !(tr->dq_semi_open));
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dll_arpi3,
+ SHU_B0_DLL_ARPI3_RG_ARPI_MCTL_EN_B0,
+ (!(tr->dq_semi_open)) && (a_cfg->rank_mode));
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dll_arpi3,
+ SHU_B1_DLL_ARPI3_RG_ARPI_DQSIEN_EN_B1, !(tr->dq_semi_open),
+ SHU_B1_DLL_ARPI3_RG_ARPI_DQ_EN_B1, !(tr->dq_semi_open),
+ SHU_B1_DLL_ARPI3_RG_ARPI_DQM_EN_B1, !(tr->dq_semi_open),
+ SHU_B1_DLL_ARPI3_RG_ARPI_DQS_EN_B1, !(tr->dq_semi_open),
+ SHU_B1_DLL_ARPI3_RG_ARPI_FB_EN_B1, !(tr->dq_semi_open));
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dll_arpi3,
+ SHU_B1_DLL_ARPI3_RG_ARPI_MCTL_EN_B1,
+ (!(tr->dq_semi_open)) && (a_cfg->rank_mode));
+ SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd2,
+ SHU_CA_CMD2_RG_ARPISM_MCK_SEL_CA_SHU, 1,
+ SHU_CA_CMD2_RG_ARPI_TX_CG_SYNC_DIS_CA, 1,
+ SHU_CA_CMD2_RG_ARPI_TX_CG_CA_EN_CA, 1,
+ SHU_CA_CMD2_RG_ARPI_TX_CG_CLK_EN_CA, 1,
+ SHU_CA_CMD2_RG_ARPI_TX_CG_CS_EN_CA, 1,
+ SHU_CA_CMD2_RG_ARPI_PD_MCTL_SEL_CA, 0);
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq2,
+ SHU_B0_DQ2_RG_ARPISM_MCK_SEL_B0_SHU, 1,
+ SHU_B0_DQ2_RG_ARPI_TX_CG_SYNC_DIS_B0, 1,
+ SHU_B0_DQ2_RG_ARPI_TX_CG_DQ_EN_B0, 1,
+ SHU_B0_DQ2_RG_ARPI_TX_CG_DQS_EN_B0, 1,
+ SHU_B0_DQ2_RG_ARPI_TX_CG_DQM_EN_B0, 1,
+ SHU_B0_DQ2_RG_ARPI_PD_MCTL_SEL_B0, 1);
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq2,
+ SHU_B1_DQ2_RG_ARPISM_MCK_SEL_B1_SHU, 1,
+ SHU_B1_DQ2_RG_ARPI_TX_CG_SYNC_DIS_B1, 1,
+ SHU_B1_DQ2_RG_ARPI_TX_CG_DQ_EN_B1, 1,
+ SHU_B1_DQ2_RG_ARPI_TX_CG_DQS_EN_B1, 1,
+ SHU_B1_DQ2_RG_ARPI_TX_CG_DQM_EN_B1, 1,
+ SHU_B1_DQ2_RG_ARPI_PD_MCTL_SEL_B1, 1);
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq7,
+ SHU_B0_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B0, 0,
+ SHU_B0_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B0, 0,
+ SHU_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0, 0);
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq7,
+ SHU_B1_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B1, 0,
+ SHU_B1_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B1, 0,
+ SHU_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1, 0);
+ SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd7,
+ SHU_CA_CMD7_R_DMTX_ARPI_CG_CS_NEW, 0,
+ SHU_CA_CMD7_R_DMTX_ARPI_CG_CMD_NEW, 0);
+}
+
+static void ana_tx_shuffle_config(ana_top_config *a_cfg)
+{
+ SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd14,
+ SHU_CA_CMD14_RG_TX_ARCA_OE_ODTEN_CG_EN_CA, 0);
+ SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd13,
+ SHU_CA_CMD13_RG_TX_ARCLK_OE_ODTEN_CG_EN_CA, 0,
+ SHU_CA_CMD13_RG_TX_ARCS_OE_ODTEN_CG_EN_CA, 0);
+
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq13,
+ SHU_B0_DQ13_RG_TX_ARDQS_OE_ODTEN_CG_EN_B0, 1,
+ SHU_B0_DQ13_RG_TX_ARDQM_OE_ODTEN_CG_EN_B0, 1,
+ SHU_B0_DQ13_RG_TX_ARDQS_READ_BASE_EN_B0, 0,
+ SHU_B0_DQ13_RG_TX_ARDQSB_READ_BASE_EN_B0, 0,
+ SHU_B0_DQ13_RG_TX_ARDQS_READ_BASE_DATA_TIE_EN_B0, 0,
+ SHU_B0_DQ13_RG_TX_ARDQSB_READ_BASE_DATA_TIE_EN_B0, 0,
+ SHU_B0_DQ13_RG_TX_ARDQ_IO_ODT_DIS_B0, a_cfg->tx_odt_dis);
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq13,
+ SHU_B1_DQ13_RG_TX_ARDQS_OE_ODTEN_CG_EN_B1, 1,
+ SHU_B1_DQ13_RG_TX_ARDQM_OE_ODTEN_CG_EN_B1, 1,
+ SHU_B1_DQ13_RG_TX_ARDQS_READ_BASE_EN_B1, 0,
+ SHU_B1_DQ13_RG_TX_ARDQSB_READ_BASE_EN_B1, 0,
+ SHU_B1_DQ13_RG_TX_ARDQS_READ_BASE_DATA_TIE_EN_B1, 0,
+ SHU_B1_DQ13_RG_TX_ARDQSB_READ_BASE_DATA_TIE_EN_B1, 0,
+ SHU_B1_DQ13_RG_TX_ARDQ_IO_ODT_DIS_B1, a_cfg->tx_odt_dis);
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq14,
+ SHU_B0_DQ14_RG_TX_ARDQ_OE_ODTEN_CG_EN_B0, 1);
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq14,
+ SHU_B1_DQ14_RG_TX_ARDQ_OE_ODTEN_CG_EN_B1, 1);
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq13,
+ SHU_B0_DQ13_RG_TX_ARDQS_MCKIO_SEL_B0, 0);
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq13,
+ SHU_B1_DQ13_RG_TX_ARDQS_MCKIO_SEL_B1, 0);
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq14,
+ SHU_B0_DQ14_RG_TX_ARDQ_MCKIO_SEL_B0, 0,
+ SHU_B0_DQ14_RG_TX_ARWCK_MCKIO_SEL_B0, 0);
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq14,
+ SHU_B1_DQ14_RG_TX_ARDQ_MCKIO_SEL_B1, 0,
+ SHU_B1_DQ14_RG_TX_ARWCK_MCKIO_SEL_B1, 0);
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq13,
+ SHU_B0_DQ13_RG_TX_ARDQ_DLY_LAT_EN_B0, 0);
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq13,
+ SHU_B1_DQ13_RG_TX_ARDQ_DLY_LAT_EN_B1, 0);
+ SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd13,
+ SHU_CA_CMD13_RG_TX_ARCA_DLY_LAT_EN_CA, 0);
+ SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd2,
+ SHU_CA_CMD2_RG_ARPI_OFFSET_LAT_EN_CA, 0,
+ SHU_CA_CMD2_RG_ARPI_OFFSET_ASYNC_EN_CA, 0);
+}
+
+static void dig_phy_shu_misc_cg_ctrl(void)
+{
+ setbits32(&ch[0].phy_ao.misc_shu_cg_ctrl0, 0x33400000);
+}
+
+static void ana_clk_div_config_setting(ana_dvfs_core *tr, ana_top_config *a_cfg)
+{
+ u8 tx_ardq_sermode=0;
+ u8 tx_arcr_sermode=0;
+ u8 ardll_sermode_b=0;
+ u8 ardll_sermode_c=0;
+
+ dramc_dbg("ANA CLOCK DIV configuration\n");
+ switch (tr->dq_p2s_ratio) {
+ case 4 :
+ tx_ardq_sermode = 1;
+ break;
+ case 8 :
+ tx_ardq_sermode = 2;
+ break;
+ case 16:
+ tx_ardq_sermode = 3;
+ break;
+ default: dramc_dbg("ERROR: tr->dq_p2s_ratio= %2d, Not support!!",tr->dq_p2s_ratio);
+ break;
+ }
+
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq14,
+ SHU_B0_DQ14_RG_TX_ARDQ_SER_MODE_B0, tx_ardq_sermode);
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq14,
+ SHU_B1_DQ14_RG_TX_ARDQ_SER_MODE_B1, tx_ardq_sermode);
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq6,
+ SHU_B0_DQ6_RG_RX_ARDQ_RANK_SEL_SER_MODE_B0, tx_ardq_sermode);
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq6,
+ SHU_B1_DQ6_RG_RX_ARDQ_RANK_SEL_SER_MODE_B1, tx_ardq_sermode);
+ SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd11,
+ SHU_CA_CMD11_RG_RX_ARCA_DES_MODE_CA, (tr->dq_p2s_ratio == 16 ) ? 3 : 2);
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq11,
+ SHU_B0_DQ11_RG_RX_ARDQ_DES_MODE_B0, (tr->dq_p2s_ratio == 16 ) ? 3 : 2);
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq11,
+ SHU_B1_DQ11_RG_RX_ARDQ_DES_MODE_B1, (tr->dq_p2s_ratio == 16 ) ? 3 : 2);
+
+ switch (tr->ca_p2s_ratio) {
+ case 2 :
+ tx_arcr_sermode = (0 + tr->ca_full_rate);
+ break;
+ case 4 :
+ tx_arcr_sermode = (1 + tr->ca_full_rate);
+ break;
+ case 8:
+ tx_arcr_sermode = (2 + tr->ca_full_rate);
+ break;
+ default: dramc_dbg("ERROR: tr->ca_p2s_ratio= %2d, Not support!!",tr->ca_p2s_ratio);
+ break;
+ }
+ SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd14,
+ SHU_CA_CMD14_RG_TX_ARCA_SER_MODE_CA, tx_arcr_sermode);
+ SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd6,
+ SHU_CA_CMD6_RG_RX_ARCMD_RANK_SEL_SER_MODE, tx_arcr_sermode);
+
+ switch (tr->dq_aamck_div) {
+ case 2 :
+ ardll_sermode_b = 1;
+ break;
+ case 4 :
+ ardll_sermode_b = 2;
+ break;
+ case 8:
+ ardll_sermode_b = 3;
+ break;
+ default: dramc_dbg("WARN: tr->dq_aamck_div= %2d, Because of dq_semi_open, It's don't care.",tr->dq_aamck_div);
+ break;
+ }
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dll1,
+ SHU_B0_DLL1_RG_ARDLL_SER_MODE_B0, ardll_sermode_b);
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dll1,
+ SHU_B1_DLL1_RG_ARDLL_SER_MODE_B1, ardll_sermode_b);
+
+ switch (tr->ca_admck_div) {
+ case 2 :
+ ardll_sermode_c = 1;
+ break;
+ case 4 :
+ ardll_sermode_c = 2;
+ break;
+ case 8:
+ ardll_sermode_c = 3;
+ break;
+ default: dramc_dbg("ERROR: tr->ca_admck_div= %2d, Not support!!",tr->ca_admck_div);
+ break;
+ }
+ dramc_set_broadcast(DRAMC_BROADCAST_OFF);
+ for (u8 chn = 0; chn < CHANNEL_MAX; chn++)
+ SET32_BITFIELDS(&ch[chn].phy_ao.shu_ca_dll1,
+ SHU_CA_DLL1_RG_ARDLL_SER_MODE_CA, ardll_sermode_c);
+
+ dramc_set_broadcast(DRAMC_BROADCAST_ON);
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq6,
+ SHU_B0_DQ6_RG_ARPI_SOPEN_EN_B0, tr->dq_semi_open,
+ SHU_B0_DQ6_RG_ARPI_OPEN_EN_B0, tr->dq_ca_open);
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq6,
+ SHU_B1_DQ6_RG_ARPI_SOPEN_EN_B1, tr->dq_semi_open,
+ SHU_B1_DQ6_RG_ARPI_OPEN_EN_B1, tr->dq_ca_open);
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq1,
+ SHU_B0_DQ1_RG_ARPI_MIDPI_EN_B0,
+ !(tr->dq_semi_open) && (!(tr->dq_ckdiv4_en)),
+ SHU_B0_DQ1_RG_ARPI_MIDPI_CKDIV4_EN_B0,
+ !(tr->dq_semi_open) && (tr->dq_ckdiv4_en),
+ SHU_B0_DQ1_RG_ARPI_MIDPI_8PH_DLY_B0, tr->ph8_dly);
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq1,
+ SHU_B1_DQ1_RG_ARPI_MIDPI_EN_B1,
+ !(tr->dq_semi_open) && (!(tr->dq_ckdiv4_en)),
+ SHU_B1_DQ1_RG_ARPI_MIDPI_CKDIV4_EN_B1,
+ !(tr->dq_semi_open) && (tr->dq_ckdiv4_en),
+ SHU_B1_DQ1_RG_ARPI_MIDPI_8PH_DLY_B1, tr->ph8_dly);
+
+ if (tr->ca_semi_open == 0) {
+ SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd6,
+ SHU_CA_CMD6_RG_ARPI_SOPEN_EN_CA, 0,
+ SHU_CA_CMD6_RG_ARPI_SOPEN_CKGEN_EN_CA, 0,
+ SHU_CA_CMD6_RG_ARPI_OFFSET_DQSIEN_CA, 0);
+ SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_dll_arpi3,
+ SHU_CA_DLL_ARPI3_RG_ARPI_FB_EN_CA, 1,
+ SHU_CA_DLL_ARPI3_RG_ARPI_CLK_EN, 1,
+ SHU_CA_DLL_ARPI3_RG_ARPI_MCTL_EN_CA, 1);
+ } else {
+ dramc_set_broadcast(DRAMC_BROADCAST_OFF);
+ for (u8 chn = 0; chn < CHANNEL_MAX; chn++) {
+ SET32_BITFIELDS(&ch[chn].phy_ao.shu_ca_cmd6,
+ SHU_CA_CMD6_RG_ARPI_SOPEN_EN_CA, 1,
+ SHU_CA_CMD6_RG_ARPI_SOPEN_CKGEN_EN_CA, 1,
+ SHU_CA_CMD6_RG_ARPI_OFFSET_DQSIEN_CA, 16);
+ SET32_BITFIELDS(&ch[chn].phy_ao.shu_ca_dll_arpi3,
+ SHU_CA_DLL_ARPI3_RG_ARPI_FB_EN_CA, 1,
+ SHU_CA_DLL_ARPI3_RG_ARPI_CLK_EN, 1);
+ }
+ SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_dll_arpi3,
+ SHU_CA_DLL_ARPI3_RG_ARPI_MCTL_EN_CA, 1);
+ SET32_BITFIELDS(&ch[1].phy_ao.shu_ca_dll_arpi3,
+ SHU_CA_DLL_ARPI3_RG_ARPI_MCTL_EN_CA, 0);
+ dramc_set_broadcast(DRAMC_BROADCAST_ON);
+ }
+ SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd6,
+ SHU_CA_CMD6_RG_ARPI_OPEN_EN_CA, tr->dq_ca_open);
+ SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd13,
+ SHU_CA_CMD13_RG_TX_ARCA_FRATE_EN_CA, tr->ca_full_rate);
+ SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd1,
+ SHU_CA_CMD1_RG_ARPI_MIDPI_8PH_DLY_CA, tr->ph8_dly);
+ SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd1,
+ SHU_CA_CMD1_RG_ARPI_MIDPI_CKDIV4_PREDIV_EN_CA, tr->ca_prediv_en);
+
+ if (tr->semi_open_ca_pick_mck_ratio == 4)
+ SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd6,
+ SHU_CA_CMD6_RG_ARPI_SOPEN_CKGEN_DIV_CA, 0);
+ else if (tr->semi_open_ca_pick_mck_ratio == 8)
+ SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd6,
+ SHU_CA_CMD6_RG_ARPI_SOPEN_CKGEN_DIV_CA, 1);
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dll1,
+ SHU_B0_DLL1_RG_ARDLL_TRACKING_CA_EN_B0, tr->dq_track_ca_en);
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dll1,
+ SHU_B1_DLL1_RG_ARDLL_TRACKING_CA_EN_B1, tr->dq_track_ca_en);
+ SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_dll_arpi2,
+ SHU_CA_DLL_ARPI2_RG_ARPI_CG_CLKIEN, 1);
+}
+
+static void ana_dll_shuffle_config(dram_freq_grp freq_group, ana_top_config *a_cfg)
+{
+ u8 gain = 0;
+ if (freq_group <= DDRFREQ_1600) {
+ gain = 2;
+ dramc_dbg("Add DLL Gain = %d\n",gain);
+ }
+
+ dramc_dbg("DLL\n");
+ if (a_cfg->dll_async_en == 1) {
+ dramc_set_broadcast(DRAMC_BROADCAST_OFF);
+ for (u8 chn = 0; chn < CHANNEL_MAX; chn++) {
+ SET32_BITFIELDS(&ch[chn].phy_ao.shu_ca_dll0,
+ SHU_CA_DLL0_RG_ARDLL_GAIN_CA,
+ (a_cfg->all_slave_en == 0) ? 6 : 7,
+ SHU_CA_DLL0_RG_ARDLL_IDLECNT_CA,
+ (a_cfg->all_slave_en == 0) ? 9 : 7,
+ SHU_CA_DLL0_RG_ARDLL_FAST_PSJP_CA,
+ !(a_cfg->all_slave_en),
+ SHU_CA_DLL0_RG_ARDLL_GEAR2_PSJP_CA, 0,
+ SHU_CA_DLL0_RG_ARDLL_FASTPJ_CK_SEL_CA,
+ a_cfg->all_slave_en);
+ SET32_BITFIELDS(&ch[chn].phy_ao.shu_ca_dll1,
+ SHU_CA_DLL1_RG_ARDLL_PHDET_OUT_SEL_CA,
+ a_cfg->all_slave_en,
+ SHU_CA_DLL1_RG_ARDLL_PHDET_IN_SWAP_CA,
+ a_cfg->all_slave_en,
+ SHU_CA_DLL1_RG_ARDLL_PGAIN_CA, 0,
+ SHU_CA_DLL1_RG_ARDLL_PSJP_EN_CA, 1,
+ SHU_CA_DLL1_RG_ARDLL_PHDIV_CA, 1,
+ SHU_CA_DLL1_RG_ARDLL_UDIV_EN_CA, 1,
+ SHU_CA_DLL1_RG_ARDLL_PS_EN_CA, 1,
+ SHU_CA_DLL1_RG_ARDLL_PD_CK_SEL_CA,
+ !(a_cfg->all_slave_en));
+ }
+ dramc_set_broadcast(DRAMC_BROADCAST_ON);
+ } else {
+ dramc_set_broadcast(DRAMC_BROADCAST_OFF);
+ SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_dll0,
+ SHU_CA_DLL0_RG_ARDLL_GAIN_CA,
+ (a_cfg->all_slave_en == 0) ? 6 + gain : 7 + gain,
+ SHU_CA_DLL0_RG_ARDLL_IDLECNT_CA,
+ (a_cfg->all_slave_en == 0) ? 9 : 7,
+ SHU_CA_DLL0_RG_ARDLL_FAST_PSJP_CA,
+ !(a_cfg->all_slave_en),
+ SHU_CA_DLL0_RG_ARDLL_GEAR2_PSJP_CA, 0,
+ SHU_CA_DLL0_RG_ARDLL_FASTPJ_CK_SEL_CA,
+ a_cfg->all_slave_en);
+ SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_dll1,
+ SHU_CA_DLL1_RG_ARDLL_PHDET_OUT_SEL_CA,
+ a_cfg->all_slave_en,
+ SHU_CA_DLL1_RG_ARDLL_PHDET_IN_SWAP_CA,
+ a_cfg->all_slave_en,
+ SHU_CA_DLL1_RG_ARDLL_PGAIN_CA, 0,
+ SHU_CA_DLL1_RG_ARDLL_PSJP_EN_CA, 1,
+ SHU_CA_DLL1_RG_ARDLL_PHDIV_CA, 1,
+ SHU_CA_DLL1_RG_ARDLL_UDIV_EN_CA, 1,
+ SHU_CA_DLL1_RG_ARDLL_PS_EN_CA, 1,
+ SHU_CA_DLL1_RG_ARDLL_PD_CK_SEL_CA,
+ !(a_cfg->all_slave_en));
+ SET32_BITFIELDS(&ch[1].phy_ao.shu_ca_dll0,
+ SHU_CA_DLL0_RG_ARDLL_GAIN_CA, 7+gain,
+ SHU_CA_DLL0_RG_ARDLL_IDLECNT_CA, 7,
+ SHU_CA_DLL0_RG_ARDLL_FAST_PSJP_CA, 0,
+ SHU_CA_DLL0_RG_ARDLL_GEAR2_PSJP_CA, 0,
+ SHU_CA_DLL0_RG_ARDLL_FASTPJ_CK_SEL_CA, 1);
+ SET32_BITFIELDS(&ch[1].phy_ao.shu_ca_dll1,
+ SHU_CA_DLL1_RG_ARDLL_PHDET_OUT_SEL_CA, 1,
+ SHU_CA_DLL1_RG_ARDLL_PHDET_IN_SWAP_CA, 1,
+ SHU_CA_DLL1_RG_ARDLL_PGAIN_CA, 0,
+ SHU_CA_DLL1_RG_ARDLL_PSJP_EN_CA, 1,
+ SHU_CA_DLL1_RG_ARDLL_PHDIV_CA, 1,
+ SHU_CA_DLL1_RG_ARDLL_UDIV_EN_CA, 1,
+ SHU_CA_DLL1_RG_ARDLL_PS_EN_CA, 1,
+ SHU_CA_DLL1_RG_ARDLL_PD_CK_SEL_CA, 0);
+ dramc_set_broadcast(DRAMC_BROADCAST_ON);
+ }
+
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dll0,
+ SHU_B0_DLL0_RG_ARDLL_GAIN_B0, 7+gain,
+ SHU_B0_DLL0_RG_ARDLL_IDLECNT_B0, 7,
+ SHU_B0_DLL0_RG_ARDLL_FAST_PSJP_B0, 0,
+ SHU_B0_DLL0_RG_ARDLL_GEAR2_PSJP_B0, 0,
+ SHU_B0_DLL0_RG_ARDLL_FASTPJ_CK_SEL_B0, 1);
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dll1,
+ SHU_B0_DLL1_RG_ARDLL_PHDET_OUT_SEL_B0, 1,
+ SHU_B0_DLL1_RG_ARDLL_PHDET_IN_SWAP_B0, 1,
+ SHU_B0_DLL1_RG_ARDLL_PGAIN_B0, 0,
+ SHU_B0_DLL1_RG_ARDLL_PSJP_EN_B0, 1,
+ SHU_B0_DLL1_RG_ARDLL_PHDIV_B0, 1,
+ SHU_B0_DLL1_RG_ARDLL_UDIV_EN_B0, 1,
+ SHU_B0_DLL1_RG_ARDLL_PS_EN_B0, 1,
+ SHU_B0_DLL1_RG_ARDLL_PD_CK_SEL_B0, 0);
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dll0,
+ SHU_B1_DLL0_RG_ARDLL_GAIN_B1, 7+gain,
+ SHU_B1_DLL0_RG_ARDLL_IDLECNT_B1, 7,
+ SHU_B1_DLL0_RG_ARDLL_FAST_PSJP_B1, 0,
+ SHU_B1_DLL0_RG_ARDLL_GEAR2_PSJP_B1, 0,
+ SHU_B1_DLL0_RG_ARDLL_FASTPJ_CK_SEL_B1, 1);
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dll1,
+ SHU_B1_DLL1_RG_ARDLL_PHDET_OUT_SEL_B1, 1,
+ SHU_B1_DLL1_RG_ARDLL_PHDET_IN_SWAP_B1, 1,
+ SHU_B1_DLL1_RG_ARDLL_PGAIN_B1, 0,
+ SHU_B1_DLL1_RG_ARDLL_PSJP_EN_B1, 1,
+ SHU_B1_DLL1_RG_ARDLL_PHDIV_B1, 1,
+ SHU_B1_DLL1_RG_ARDLL_UDIV_EN_B1, 1,
+ SHU_B1_DLL1_RG_ARDLL_PS_EN_B1, 1,
+ SHU_B1_DLL1_RG_ARDLL_PD_CK_SEL_B1, 0);
+}
+
+static void ana_rx_shuffle_config(dramc_subsys_config *subsys)
+{
+ u8 rdqs_se_en;
+ u8 dqsien_mode;
+ u8 rank_mode;
+
+ rdqs_se_en = 0;
+ dqsien_mode = subsys->dfs_gp->dqsien_mode;
+ rank_mode = subsys->a_cfg->rank_mode;
+
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq10,
+ SHU_B0_DQ10_RG_RX_ARDQS_SE_EN_B0, rdqs_se_en,
+ SHU_B0_DQ10_RG_RX_ARDQS_DQSIEN_MODE_B0, dqsien_mode,
+ SHU_B0_DQ10_RG_RX_ARDQS_DLY_LAT_EN_B0, 1,
+ SHU_B0_DQ10_RG_RX_ARDQS_RANK_SEL_LAT_EN_B0, rank_mode,
+ SHU_B0_DQ10_RG_RX_ARDQS_DQSIEN_RANK_SEL_LAT_EN_B0, rank_mode);
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq11,
+ SHU_B0_DQ11_RG_RX_ARDQ_RANK_SEL_SER_EN_B0, rank_mode,
+ SHU_B0_DQ11_RG_RX_ARDQ_RANK_SEL_LAT_EN_B0, rank_mode);
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq2,
+ SHU_B0_DQ2_RG_ARPI_OFFSET_LAT_EN_B0, rank_mode,
+ SHU_B0_DQ2_RG_ARPI_OFFSET_ASYNC_EN_B0, rank_mode);
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq10,
+ SHU_B1_DQ10_RG_RX_ARDQS_SE_EN_B1, rdqs_se_en,
+ SHU_B1_DQ10_RG_RX_ARDQS_DQSIEN_MODE_B1, dqsien_mode,
+ SHU_B1_DQ10_RG_RX_ARDQS_DLY_LAT_EN_B1, 1,
+ SHU_B1_DQ10_RG_RX_ARDQS_RANK_SEL_LAT_EN_B1, rank_mode,
+ SHU_B1_DQ10_RG_RX_ARDQS_DQSIEN_RANK_SEL_LAT_EN_B1, rank_mode);
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq11,
+ SHU_B1_DQ11_RG_RX_ARDQ_RANK_SEL_SER_EN_B1, rank_mode,
+ SHU_B1_DQ11_RG_RX_ARDQ_RANK_SEL_LAT_EN_B1, rank_mode);
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq2,
+ SHU_B1_DQ2_RG_ARPI_OFFSET_LAT_EN_B1, rank_mode,
+ SHU_B1_DQ2_RG_ARPI_OFFSET_ASYNC_EN_B1, rank_mode);
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq10,
+ SHU_B0_DQ10_RG_RX_ARDQS_DLY_LAT_EN_B0, 0);
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq2,
+ SHU_B0_DQ2_RG_ARPI_OFFSET_LAT_EN_B0, 0);
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq10,
+ SHU_B1_DQ10_RG_RX_ARDQS_DLY_LAT_EN_B1, 0);
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq2,
+ SHU_B1_DQ2_RG_ARPI_OFFSET_LAT_EN_B1, 0);
+ SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd10,
+ SHU_CA_CMD10_RG_RX_ARCLK_RANK_SEL_LAT_EN_CA, 1,
+ SHU_CA_CMD10_RG_RX_ARCLK_DQSIEN_RANK_SEL_LAT_EN_CA, 1);
+ SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd11,
+ SHU_CA_CMD11_RG_RX_ARCA_RANK_SEL_LAT_EN_CA, 1);
+}
+
+static void ana_config_nonshuffle(dram_freq_grp freq_group, ana_top_config *a_cfg)
+{
+ suspend_on();
+ spm_control(a_cfg);
+ ana_tx_nonshuffle_config(a_cfg);
+ ana_rx_nonshuffle_config();
+ dig_dcm_nonshuffle_config();
+ ana_imp_configure();
+ ana_dll_non_shuffle_config(freq_group, a_cfg);
+}
+
+static void ana_config_shuffle(dram_freq_grp freq_group, dramc_subsys_config *subsys)
+{
+ ana_top_config *a_cfg = subsys->a_cfg;
+ ana_dvfs_core *dvfs_core = subsys->dvfs_core;
+
+ ana_pll_shuffle_Config(dvfs_core);
+ ana_arpi_shuffle_config(a_cfg, dvfs_core);
+ ana_tx_shuffle_config(a_cfg);
+ ana_rx_shuffle_config(subsys);
+ dig_phy_shu_misc_cg_ctrl();
+ ana_clk_div_config_setting(dvfs_core, a_cfg);
+ ana_dll_shuffle_config(freq_group, a_cfg);
+}
+
+static void ana_phy_config(dram_freq_grp freq_group, dramc_subsys_config *subsys)
+{
+ ana_top_config *a_cfg = subsys->a_cfg;
+
+ ana_config_nonshuffle(freq_group, a_cfg);
+ ana_config_shuffle(freq_group, subsys);
+}
+
+static void ana_clockoff_sequence(void)
+{
+ SET32_BITFIELDS(&ch[0].phy_ao.misc_cg_ctrl0,
+ MISC_CG_CTRL0_CLK_MEM_SEL, 0,
+ MISC_CG_CTRL0_W_CHG_MEM, 1);
+ udelay(1);
+ SET32_BITFIELDS(&ch[0].phy_ao.misc_cg_ctrl0,
+ MISC_CG_CTRL0_W_CHG_MEM, 0);
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dll1,
+ SHU_B0_DLL1_RG_ARDLL_PHDET_EN_B0, 0);
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dll1,
+ SHU_B1_DLL1_RG_ARDLL_PHDET_EN_B1, 0);
+ dramc_set_broadcast(DRAMC_BROADCAST_OFF);
+ for (u8 chn = 0; chn < CHANNEL_MAX; chn++)
+ SET32_BITFIELDS(&ch[chn].phy_ao.shu_ca_dll1,
+ SHU_CA_DLL1_RG_ARDLL_PHDET_EN_CA, 0);
+
+ dramc_set_broadcast(DRAMC_BROADCAST_ON);
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dll_arpi2,
+ SHU_B0_DLL_ARPI2_RG_ARPI_CG_MCK_B0, 0x1,
+ SHU_B0_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_B0, 0x1,
+ SHU_B0_DLL_ARPI2_RG_ARPI_CG_MCTL_B0, 0x1,
+ SHU_B0_DLL_ARPI2_RG_ARPI_CG_FB_B0, 0x1,
+ SHU_B0_DLL_ARPI2_RG_ARPI_CG_DQS_B0, 0x1,
+ SHU_B0_DLL_ARPI2_RG_ARPI_CG_DQM_B0, 0x1,
+ SHU_B0_DLL_ARPI2_RG_ARPI_CG_DQ_B0, 0x1,
+ SHU_B0_DLL_ARPI2_RG_ARPI_CG_DQSIEN_B0, 0x1,
+ SHU_B0_DLL_ARPI2_RG_ARPI_MPDIV_CG_B0, 0x1);
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dll_arpi2,
+ SHU_B1_DLL_ARPI2_RG_ARPI_CG_MCK_B1, 0x1,
+ SHU_B1_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_B1, 0x1,
+ SHU_B1_DLL_ARPI2_RG_ARPI_CG_MCTL_B1, 0x1,
+ SHU_B1_DLL_ARPI2_RG_ARPI_CG_FB_B1, 0x1,
+ SHU_B1_DLL_ARPI2_RG_ARPI_CG_DQS_B1, 0x1,
+ SHU_B1_DLL_ARPI2_RG_ARPI_CG_DQM_B1, 0x1,
+ SHU_B1_DLL_ARPI2_RG_ARPI_CG_DQ_B1, 0x1,
+ SHU_B1_DLL_ARPI2_RG_ARPI_CG_DQSIEN_B1, 0x1,
+ SHU_B1_DLL_ARPI2_RG_ARPI_MPDIV_CG_B1, 0x1);
+ SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_dll_arpi2,
+ SHU_CA_DLL_ARPI2_RG_ARPI_CG_MCK_CA, 0x1,
+ SHU_CA_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_CA, 0x1,
+ SHU_CA_DLL_ARPI2_RG_ARPI_CG_MCTL_CA, 0x1,
+ SHU_CA_DLL_ARPI2_RG_ARPI_CG_FB_CA, 0x1,
+ SHU_CA_DLL_ARPI2_RG_ARPI_CG_CS, 0x1,
+ SHU_CA_DLL_ARPI2_RG_ARPI_CG_CLK, 0x1,
+ SHU_CA_DLL_ARPI2_RG_ARPI_CG_CMD, 0x1,
+ SHU_CA_DLL_ARPI2_RG_ARPI_CG_CLKIEN, 0x1,
+ SHU_CA_DLL_ARPI2_RG_ARPI_MPDIV_CG_CA, 0x1);
+ SET32_BITFIELDS(&ch[0].phy_ao.shu_pll2,
+ SHU_PLL2_RG_RPHYPLL_ADA_MCK8X_EN_SHU, 0);
+ SET32_BITFIELDS(&ch[0].phy_ao.phypll2,
+ PHYPLL2_RG_RPHYPLL_AD_MCK8X_EN, 0,
+ PHYPLL2_RG_RPHYPLL_ADA_MCK8X_EN, 0);
+ SET32_BITFIELDS(&ch[0].phy_ao.phypll0, PHYPLL0_RG_RPHYPLL_EN, 0);
+ SET32_BITFIELDS(&ch[0].phy_ao.phypll2, PHYPLL2_RG_RPHYPLL_RESETB, 0);
+}
+
+static void ana_pll_sequence(void)
+{
+ SET32_BITFIELDS(&ch[0].phy_ao.phypll2, PHYPLL2_RG_RPHYPLL_RESETB, 1);
+ SET32_BITFIELDS(&ch[0].phy_ao.phypll0, PHYPLL0_RG_RPHYPLL_EN, 1);
+ udelay(20);
+}
+
+static void ana_midpi_sequence(ana_dvfs_core *dvfs_core)
+{
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq1,
+ SHU_B0_DQ1_RG_ARPI_MIDPI_LDO_VREF_SEL_B0, 1);
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq1,
+ SHU_B1_DQ1_RG_ARPI_MIDPI_LDO_VREF_SEL_B1, 1);
+ SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd1,
+ SHU_CA_CMD1_RG_ARPI_MIDPI_LDO_VREF_SEL_CA, 1);
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dll_arpi2,
+ SHU_B0_DLL_ARPI2_RG_ARPI_MPDIV_CG_B0, 1,
+ SHU_B0_DLL_ARPI2_RG_ARPI_CG_FB_B0, 1);
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dll_arpi2,
+ SHU_B1_DLL_ARPI2_RG_ARPI_MPDIV_CG_B1, 1,
+ SHU_B1_DLL_ARPI2_RG_ARPI_CG_FB_B1, 1);
+ SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_dll_arpi2,
+ SHU_CA_DLL_ARPI2_RG_ARPI_MPDIV_CG_CA, 1,
+ SHU_CA_DLL_ARPI2_RG_ARPI_CG_FB_CA, 1);
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dll_arpi2,
+ SHU_B0_DLL_ARPI2_RG_ARPI_CG_MCK_B0, 0x1,
+ SHU_B0_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_B0, 0x1,
+ SHU_B0_DLL_ARPI2_RG_ARPI_CG_MCTL_B0, 0x1,
+ SHU_B0_DLL_ARPI2_RG_ARPI_CG_FB_B0, 0x1,
+ SHU_B0_DLL_ARPI2_RG_ARPI_CG_DQS_B0, 0x1,
+ SHU_B0_DLL_ARPI2_RG_ARPI_CG_DQM_B0, 0x1,
+ SHU_B0_DLL_ARPI2_RG_ARPI_CG_DQ_B0, 0x1,
+ SHU_B0_DLL_ARPI2_RG_ARPI_CG_DQSIEN_B0, 0x1,
+ SHU_B0_DLL_ARPI2_RG_ARPI_MPDIV_CG_B0, 0x1);
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dll_arpi2,
+ SHU_B1_DLL_ARPI2_RG_ARPI_CG_MCK_B1, 0x1,
+ SHU_B1_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_B1, 0x1,
+ SHU_B1_DLL_ARPI2_RG_ARPI_CG_MCTL_B1, 0x1,
+ SHU_B1_DLL_ARPI2_RG_ARPI_CG_FB_B1, 0x1,
+ SHU_B1_DLL_ARPI2_RG_ARPI_CG_DQS_B1, 0x1,
+ SHU_B1_DLL_ARPI2_RG_ARPI_CG_DQM_B1, 0x1,
+ SHU_B1_DLL_ARPI2_RG_ARPI_CG_DQ_B1, 0x1,
+ SHU_B1_DLL_ARPI2_RG_ARPI_CG_DQSIEN_B1, 0x1,
+ SHU_B1_DLL_ARPI2_RG_ARPI_MPDIV_CG_B1, 0x1);
+ SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_dll_arpi2,
+ SHU_CA_DLL_ARPI2_RG_ARPI_CG_MCK_CA, 0x1,
+ SHU_CA_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_CA, 0x1,
+ SHU_CA_DLL_ARPI2_RG_ARPI_CG_MCTL_CA, 0x1,
+ SHU_CA_DLL_ARPI2_RG_ARPI_CG_FB_CA, 0x1,
+ SHU_CA_DLL_ARPI2_RG_ARPI_CG_CS, 0x1,
+ SHU_CA_DLL_ARPI2_RG_ARPI_CG_CLK, 0x1,
+ SHU_CA_DLL_ARPI2_RG_ARPI_CG_CMD, 0x1,
+ SHU_CA_DLL_ARPI2_RG_ARPI_CG_CLKIEN, 0x1,
+ SHU_CA_DLL_ARPI2_RG_ARPI_MPDIV_CG_CA, 0x1);
+ SET32_BITFIELDS(&ch[0].phy_ao.shu_pll2,
+ SHU_PLL2_RG_RPHYPLL_ADA_MCK8X_EN_SHU, 0);
+ SET32_BITFIELDS(&ch[0].phy_ao.phypll2,
+ PHYPLL2_RG_RPHYPLL_AD_MCK8X_EN, 0,
+ PHYPLL2_RG_RPHYPLL_ADA_MCK8X_EN, 0);
+ SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd1,
+ SHU_CA_CMD1_RG_ARPI_MIDPI_EN_CA, !(dvfs_core->ca_ckdiv4_en),
+ SHU_CA_CMD1_RG_ARPI_MIDPI_CKDIV4_EN_CA, dvfs_core->ca_ckdiv4_en);
+ SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd1,
+ SHU_CA_CMD1_RG_ARPI_MIDPI_CKDIV4_PREDIV_EN_CA, dvfs_core->ca_prediv_en);
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[0].b0_shu_midpi_ctrl,
+ B0_SHU_MIDPI_CTRL_MIDPI_ENABLE_B0,
+ (!(dvfs_core->dq_semi_open)) && (!(dvfs_core->dq_ckdiv4_en)),
+ B0_SHU_MIDPI_CTRL_MIDPI_DIV4_ENABLE_B0,
+ (!(dvfs_core->dq_semi_open)) && (dvfs_core->dq_ckdiv4_en));
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[1].b0_shu_midpi_ctrl,
+ B1_SHU_MIDPI_CTRL_MIDPI_ENABLE_B1,
+ (!(dvfs_core->dq_semi_open)) && (!(dvfs_core->dq_ckdiv4_en)),
+ B1_SHU_MIDPI_CTRL_MIDPI_DIV4_ENABLE_B1,
+ (!(dvfs_core->dq_semi_open)) && (dvfs_core->dq_ckdiv4_en));
+ SET32_BITFIELDS(&ch[0].phy_ao.ca_shu_midpi_ctrl,
+ CA_SHU_MIDPI_CTRL_MIDPI_ENABLE_CA, !(dvfs_core->ca_ckdiv4_en),
+ CA_SHU_MIDPI_CTRL_MIDPI_DIV4_ENABLE_CA, dvfs_core->ca_ckdiv4_en);
+ SET32_BITFIELDS(&ch[0].phy_ao.ca_dll_arpi0,
+ CA_DLL_ARPI0_RG_ARPI_RESETB_CA, 0);
+ SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dll_arpi0,
+ B0_DLL_ARPI0_RG_ARPI_RESETB_B0, 0);
+ SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dll_arpi0,
+ B1_DLL_ARPI0_RG_ARPI_RESETB_B1, 0);
+ SET32_BITFIELDS(&ch[0].phy_ao.ca_dll_arpi0,
+ CA_DLL_ARPI0_RG_ARPI_RESETB_CA, 1);
+ SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dll_arpi0,
+ B0_DLL_ARPI0_RG_ARPI_RESETB_B0, 1);
+ SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dll_arpi0,
+ B1_DLL_ARPI0_RG_ARPI_RESETB_B1, 1);
+ SET32_BITFIELDS(&ch[0].phy_ao.shu_pll2,
+ SHU_PLL2_RG_RPHYPLL_ADA_MCK8X_EN_SHU, 1);
+ SET32_BITFIELDS(&ch[0].phy_ao.phypll2,
+ PHYPLL2_RG_RPHYPLL_AD_MCK8X_EN, 1,
+ PHYPLL2_RG_RPHYPLL_ADA_MCK8X_EN, 1);
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dll_arpi2,
+ SHU_B0_DLL_ARPI2_RG_ARPI_CG_MCK_B0, 0x0,
+ SHU_B0_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_B0, 0x0,
+ SHU_B0_DLL_ARPI2_RG_ARPI_CG_MCTL_B0, 0x0,
+ SHU_B0_DLL_ARPI2_RG_ARPI_CG_FB_B0, 0x0,
+ SHU_B0_DLL_ARPI2_RG_ARPI_CG_DQS_B0, 0x0,
+ SHU_B0_DLL_ARPI2_RG_ARPI_CG_DQM_B0, 0x0,
+ SHU_B0_DLL_ARPI2_RG_ARPI_CG_DQ_B0, 0x0,
+ SHU_B0_DLL_ARPI2_RG_ARPI_CG_DQSIEN_B0, 0x0,
+ SHU_B0_DLL_ARPI2_RG_ARPI_MPDIV_CG_B0, dvfs_core->dq_semi_open);
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dll_arpi2,
+ SHU_B1_DLL_ARPI2_RG_ARPI_CG_MCK_B1, 0x0,
+ SHU_B1_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_B1, 0x0,
+ SHU_B1_DLL_ARPI2_RG_ARPI_CG_MCTL_B1, 0x0,
+ SHU_B1_DLL_ARPI2_RG_ARPI_CG_FB_B1, 0x0,
+ SHU_B1_DLL_ARPI2_RG_ARPI_CG_DQS_B1, 0x0,
+ SHU_B1_DLL_ARPI2_RG_ARPI_CG_DQM_B1, 0x0,
+ SHU_B1_DLL_ARPI2_RG_ARPI_CG_DQ_B1, 0x0,
+ SHU_B1_DLL_ARPI2_RG_ARPI_CG_DQSIEN_B1, 0x0,
+ SHU_B1_DLL_ARPI2_RG_ARPI_MPDIV_CG_B1, dvfs_core->dq_semi_open);
+ SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_dll_arpi2,
+ SHU_CA_DLL_ARPI2_RG_ARPI_CG_MCK_CA, 0x0,
+ SHU_CA_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_CA, 0x0,
+ SHU_CA_DLL_ARPI2_RG_ARPI_CG_MCTL_CA, 0x0,
+ SHU_CA_DLL_ARPI2_RG_ARPI_CG_FB_CA, 0x0,
+ SHU_CA_DLL_ARPI2_RG_ARPI_CG_CS, 0x0,
+ SHU_CA_DLL_ARPI2_RG_ARPI_CG_CLK, 0x0,
+ SHU_CA_DLL_ARPI2_RG_ARPI_CG_CMD, 0x0,
+ SHU_CA_DLL_ARPI2_RG_ARPI_CG_CLKIEN, 0x0,
+ SHU_CA_DLL_ARPI2_RG_ARPI_MPDIV_CG_CA, 0x0);
+}
+
+static void ana_clock_switch(ana_dvfs_core *a_dvfs_cor)
+{
+ if (a_dvfs_cor->dq_ca_open) {
+ SET32_BITFIELDS(&ch[0].phy_ao.misc_cg_ctrl0,
+ MISC_CG_CTRL0_RESERVED_MISC_CG_CTRL0_BIT3_1, 1);
+ udelay(1);
+ SET32_BITFIELDS(&ch[0].phy_ao.misc_cg_ctrl0,
+ MISC_CG_CTRL0_RESERVED_MISC_CG_CTRL0_BIT3_1, 0);
+ }
+ dramc_set_broadcast(DRAMC_BROADCAST_OFF);
+ for (u8 chn = 0; chn < CHANNEL_MAX; chn++)
+ SET32_BITFIELDS(&ch[chn].phy_ao.misc_ckmux_sel,
+ MISC_CKMUX_SEL_R_PHYCTRLDCM, 1,
+ MISC_CKMUX_SEL_R_PHYCTRLMUX, 1);
+
+ dramc_set_broadcast(DRAMC_BROADCAST_ON);
+ SET32_BITFIELDS(&ch[0].phy_ao.misc_cg_ctrl0,
+ MISC_CG_CTRL0_CLK_MEM_SEL, 1,
+ MISC_CG_CTRL0_W_CHG_MEM, 1);
+
+ udelay(1);
+ SET32_BITFIELDS(&ch[0].phy_ao.misc_cg_ctrl0,
+ MISC_CG_CTRL0_W_CHG_MEM, 0);
+ SET32_BITFIELDS(&ch[0].phy_ao.misc_cg_ctrl0,
+ MISC_CG_CTRL0_RG_FREERUN_MCK_CG, 1);
+ if (a_dvfs_cor->dq_ca_open)
+ SET32_BITFIELDS(&ch[0].phy_ao.misc_cg_ctrl0,
+ MISC_CG_CTRL0_RESERVED_MISC_CG_CTRL0_BIT7, 1);
+}
+
+static void ana_dll_sequence(ana_dvfs_core *dvfs_core, ana_top_config *a_cfg)
+{
+ u8 dll_async_en;
+ u8 all_slave_en;
+
+ dll_async_en = a_cfg->dll_async_en;
+ all_slave_en = a_cfg->all_slave_en;
+
+ dramc_dbg("[ANA_INIT] DLL >>\n");
+ SET32_BITFIELDS(&ch[0].phy_ao.ca_cmd8,
+ CA_CMD8_RG_ARDLL_RESETB_CA, 1);
+ SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq8,
+ B0_DQ8_RG_ARDLL_RESETB_B0, 1);
+ SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq8,
+ B1_DQ8_RG_ARDLL_RESETB_B1, 1);
+ if (all_slave_en == 1) {
+ dramc_set_broadcast(DRAMC_BROADCAST_OFF);
+ for (u8 chn = 0; chn < CHANNEL_MAX; chn++)
+ SET32_BITFIELDS(&ch[chn].phy_ao.shu_ca_dll1,
+ SHU_CA_DLL1_RG_ARDLL_PHDET_EN_CA, 1);
+
+ dramc_set_broadcast(DRAMC_BROADCAST_ON);
+ udelay(1);
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dll1,
+ SHU_B0_DLL1_RG_ARDLL_PHDET_EN_B0, !(dvfs_core->dq_semi_open));
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dll1,
+ SHU_B1_DLL1_RG_ARDLL_PHDET_EN_B1, !(dvfs_core->dq_semi_open));
+ udelay(1);
+ } else {
+ dramc_set_broadcast(DRAMC_BROADCAST_OFF);
+ if (dll_async_en == 1) {
+ for (u8 chn = 0; chn < CHANNEL_MAX; chn++)
+ SET32_BITFIELDS(&ch[chn].phy_ao.shu_ca_dll1,
+ SHU_CA_DLL1_RG_ARDLL_PHDET_EN_CA, 1);
+ udelay(1);
+ } else {
+ SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_dll1,
+ SHU_CA_DLL1_RG_ARDLL_PHDET_EN_CA, 1);
+ udelay(1);
+ SET32_BITFIELDS(&ch[1].phy_ao.shu_ca_dll1,
+ SHU_CA_DLL1_RG_ARDLL_PHDET_EN_CA, 1);
+ udelay(1);
+ }
+ dramc_set_broadcast(DRAMC_BROADCAST_ON);
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dll1,
+ SHU_B0_DLL1_RG_ARDLL_PHDET_EN_B0, !(dvfs_core->dq_semi_open));
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dll1,
+ SHU_B1_DLL1_RG_ARDLL_PHDET_EN_B1, !(dvfs_core->dq_semi_open));
+ udelay(1);
+ }
+}
+
+void ana_clk_div_config( ana_dvfs_core *tr, dvfs_group_config *dfs)
+{
+ u32 semi_open_fmin = 300;
+ u32 semi_open_fmax = 500;
+ u32 pi_fmin = 600;
+ u32 dq_pick;
+ u32 ca_pick;
+ u32 ca_mckio;
+ u32 mckio_semi = 0;
+ u16 data_rate = dfs->data_rate;
+ tr->dq_p2s_ratio = dfs->dq_p2s_ratio;
+ tr->ckr = dfs->ckr;
+
+ tr->ca_p2s_ratio = tr->dq_p2s_ratio/tr->ckr;
+ tr->dq_ca_open = ( data_rate < (semi_open_fmin * 2)) ? 1 : 0;
+ tr->dq_semi_open = ( data_rate/2 < pi_fmin) ? (1-tr->dq_ca_open) :
+ ((data_rate <= semi_open_fmax*2) ? (1-tr->dq_ca_open) : 0);
+ tr->ca_semi_open = (( data_rate/(tr->ckr*2) < pi_fmin) ?
+ ((data_rate/(tr->ckr*2) > semi_open_fmax) ? 0 :
+ (((tr->ca_p2s_ratio>2)||(tr->dq_semi_open)) * (1-tr->dq_ca_open))) :
+ tr->dq_semi_open);
+ tr->ca_full_rate = (tr->dq_ca_open == 1) ? ((tr->ckr>1)?1:0) :
+ ((tr->dq_semi_open*tr->ca_semi_open*(tr->ckr>>1)) +
+ (( data_rate/(tr->ckr*2) < pi_fmin) ? (1-tr->ca_semi_open) : 0));
+ tr->dq_ckdiv4_en = ( tr->dq_semi_open == 1) ? 0 :
+ ((( (data_rate/2) < 1200) ? 1 : 0) * (1-tr->dq_ca_open)) ;
+
+ ca_mckio = (data_rate/(tr->ckr*2))*(1+tr->ca_full_rate);
+ dq_pick = (tr->dq_semi_open == 1) ? 0 : (data_rate/2) ;
+ ca_pick = (tr->ca_semi_open == 1) ? ca_mckio*2 : ((ca_mckio>=pi_fmin) ?
+ ca_mckio : (( ca_mckio >= (pi_fmin/2)) ? ca_mckio*2 : ca_mckio *4));
+ tr->ca_ckdiv4_en = ((ca_pick < 1200) ? 1 : 0) * ( 1- tr->dq_ca_open) ;
+ tr->ca_prediv_en = (data_rate >= 4800) ? 1 : 0 ;
+
+ if (data_rate <= 1866)
+ tr->ph8_dly = 0;
+ else if (data_rate <= 2400)
+ tr->ph8_dly = 0x11;
+ else if (data_rate <= 3200)
+ tr->ph8_dly = 0xc;
+ else if (data_rate <= 3733)
+ tr->ph8_dly = 0x9;
+ else
+ tr->ph8_dly = 0x7;
+
+ tr->semi_open_ca_pick_mck_ratio = ( mckio_semi == 0) ?
+ 0 : (ca_pick*tr->dq_p2s_ratio)/data_rate ;
+ tr->dq_aamck_div = (tr->dq_semi_open == 0) ?
+ ((tr->dq_p2s_ratio/2)*(1-tr->dq_semi_open)) : 0;
+ tr->ca_admck_div = ca_pick/(data_rate/tr->dq_p2s_ratio);
+ tr->dq_track_ca_en = 0 ;
+ tr->pll_freq = ((dq_pick * 2 * (tr->dq_ckdiv4_en+1)) > (ca_pick * 2 *(tr->ca_ckdiv4_en + 1))) ?
+ (dq_pick*2*(tr->dq_ckdiv4_en+1)) : (ca_pick*2*(tr->ca_ckdiv4_en+1));
+
+ if (data_rate==2400)
+ tr->pll_freq = 2366;
+ else if (data_rate==1200)
+ tr->pll_freq = 2288;
+ else if (data_rate==3200 || data_rate==1600)
+ tr->pll_freq = 3068;
+ else if (data_rate==800)
+ tr->pll_freq = 3016;
+ else if (data_rate==400)
+ tr->pll_freq = 4000;
+}
+
+static void ana_init_sequence(ana_dvfs_core *dvfs_core, ana_top_config *a_cfg)
+{
+ ana_pll_sequence();
+ ana_midpi_sequence(dvfs_core);
+ ana_clock_switch(dvfs_core);
+ ana_dll_sequence(dvfs_core,a_cfg);
+}
+
+void ana_init(const struct ddr_cali *cali, dramc_subsys_config *subsys)
+{
+ dram_freq_grp freq_group = cali->freq_group;
+
+ dramc_subsys_pre_config(freq_group, subsys);
+ dramc_dbg("ANA_INIT\n");
+
+ SET32_BITFIELDS(&ch[0].phy_ao.ca_cmd2,
+ CA_CMD2_RG_TX_ARCMD_OE_DIS_CA, 1,
+ CA_CMD2_RG_TX_ARCA_OE_TIE_SEL_CA, 0,
+ CA_CMD2_RG_TX_ARCA_OE_TIE_EN_CA, 0xff);
+ ana_clockoff_sequence();
+ ana_phy_config(freq_group, subsys);
+ ana_init_sequence(subsys->dvfs_core, subsys->a_cfg);
+ SET32_BITFIELDS(&ch[0].phy_ao.ca_cmd2,
+ CA_CMD2_RG_TX_ARCMD_OE_DIS_CA, 0,
+ CA_CMD2_RG_TX_ARCA_OE_TIE_SEL_CA, 1,
+ CA_CMD2_RG_TX_ARCA_OE_TIE_EN_CA, 0xff);
+ single_end_dramc_post_config(subsys->lp4_init->lp4y_en);
+}
diff --git a/src/soc/mediatek/mt8192/dramc_pi_basic_api.c b/src/soc/mediatek/mt8192/dramc_pi_basic_api.c
index 1d6b6c2..d32c268 100644
--- a/src/soc/mediatek/mt8192/dramc_pi_basic_api.c
+++ b/src/soc/mediatek/mt8192/dramc_pi_basic_api.c
@@ -3742,6 +3742,12 @@
static void dramc_setting(const struct ddr_cali *cali)
{
+ dramc_subsys_config subsys;
+ ana_top_config ana_top_p;
+ struct gating_config gat_config;
+ static ana_dvfs_core ana_dvfs;
+ static dram_config lp4_config;
+ dvfs_group_config dvfs_config;
dram_freq_grp freq_group = cali->freq_group;
dramc_set_broadcast(DRAMC_BROADCAST_ON);
@@ -3766,6 +3772,13 @@
return;
}
+ resetb_pull_dn();
+ subsys.a_cfg = &ana_top_p;
+ subsys.dvfs_core = &ana_dvfs;
+ subsys.lp4_init = &lp4_config;
+ subsys.dfs_gp = &dvfs_config;
+ subsys.gat_c = &gat_config;
+ ana_init(cali, &subsys);
update_initial_settings(cali);
dramc_set_broadcast(DRAMC_BROADCAST_OFF);
}
diff --git a/src/soc/mediatek/mt8192/dramc_subsys_config.c b/src/soc/mediatek/mt8192/dramc_subsys_config.c
new file mode 100644
index 0000000..146e073
--- /dev/null
+++ b/src/soc/mediatek/mt8192/dramc_subsys_config.c
@@ -0,0 +1,134 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/dramc_pi_api.h>
+#include <soc/dramc_register.h>
+
+static u8 get_dram_RL_WL_mr_field_config(dram_freq_grp freq_group)
+{
+ u8 mr2_rl_wl = 2;
+
+ switch(freq_group) {
+ case DDRFREQ_400:
+ case DDRFREQ_600:
+ case DDRFREQ_800:
+ mr2_rl_wl = 2;
+ break;
+ case DDRFREQ_933:
+ mr2_rl_wl = 3;
+ break;
+ case DDRFREQ_1200:
+ mr2_rl_wl = 4;
+ break;
+ case DDRFREQ_1600:
+ mr2_rl_wl = 5;
+ break;
+ case DDRFREQ_2133:
+ mr2_rl_wl = 7;
+ break;
+ default:
+ dramc_dbg("ERROR: Unexpected freq:0x%x\n", freq_group);
+ break;
+ }
+
+ return mr2_rl_wl;
+}
+
+void dram_configure(dram_freq_grp freq_group, dram_config *tr)
+{
+ tr->mr_wl = get_dram_RL_WL_mr_field_config(freq_group);
+ tr->dbi_wr = 0;
+ tr->dbi_rd = 0;
+ tr->lp4y_en = 0;
+ tr->work_fsp = (freq_group > DDRFREQ_1200) ? 1 : 0;
+}
+
+void dramc_subsys_pre_config(dram_freq_grp freq_group, dramc_subsys_config *subsys)
+{
+ ana_top_config *a_cfg = subsys->a_cfg;
+ dram_config *lp4_init = subsys->lp4_init;
+ dvfs_group_config *dfs_gp = subsys->dfs_gp;
+
+ subsys->freq_group = freq_group;
+ dfs_gp->ckr = 1;
+ dfs_gp->dqsien_mode = 1;
+ lp4_init->ex_row_en[RANK_0] = (get_row_width_from_emi(RANK_0) >= 18) ? 1 : 0;
+ lp4_init->ex_row_en[RANK_1] = (get_row_width_from_emi(RANK_1) >= 18) ? 1 : 0;
+ lp4_init->lp4y_en = 0;
+ a_cfg->new_8x_mode = 1;
+ a_cfg->aphy_comb_en = 1 ;
+ a_cfg->dll_idle_mode = 1;
+ a_cfg->rank_mode = 1;
+ a_cfg->dll_async_en = 0;
+
+ switch (freq_group) {
+ case DDRFREQ_400:
+ dfs_gp->data_rate = 800;
+ dfs_gp->dq_p2s_ratio = 4;
+ break;
+ case DDRFREQ_600:
+ dfs_gp->data_rate = 1200;
+ dfs_gp->dq_p2s_ratio = 8;
+ break;
+ case DDRFREQ_800:
+ dfs_gp->data_rate = 1600;
+ dfs_gp->dq_p2s_ratio = 8;
+ break;
+ case DDRFREQ_933:
+ dfs_gp->data_rate = 1866;
+ dfs_gp->dq_p2s_ratio = 8;
+ break;
+ case DDRFREQ_1200:
+ dfs_gp->data_rate = 2400;
+ dfs_gp->dq_p2s_ratio = 8;
+ break;
+ case DDRFREQ_1600:
+ dfs_gp->data_rate = 3200;
+ dfs_gp->dq_p2s_ratio = 8;
+ break;
+ case DDRFREQ_2133:
+ dfs_gp->data_rate = 4266;
+ dfs_gp->dq_p2s_ratio = 8;
+ break;
+ default:
+ die("Invalid DDR frequency group %u\n", freq_group);
+ return;
+ }
+
+ dram_configure(freq_group, lp4_init);
+
+ a_cfg->all_slave_en = (freq_group <= DDRFREQ_933) ? 1 : 0;
+ a_cfg->tx_odt_dis = (freq_group <= DDRFREQ_1200) ? 1 : 0 ;
+
+ ana_clk_div_config(subsys->dvfs_core, subsys->dfs_gp);
+}
+
+void single_end_dramc_post_config(u8 lp4y_en)
+{
+ SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd13,
+ SHU_CA_CMD13_RG_TX_ARCLKB_OE_TIE_SEL_CA, lp4y_en,
+ SHU_CA_CMD13_RG_TX_ARCLKB_OE_TIE_EN_CA, lp4y_en);
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq13,
+ SHU_B0_DQ13_RG_TX_ARDQSB_OE_TIE_SEL_B0, lp4y_en,
+ SHU_B0_DQ13_RG_TX_ARDQSB_OE_TIE_EN_B0, lp4y_en);
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq13,
+ SHU_B1_DQ13_RG_TX_ARDQSB_OE_TIE_SEL_B1, lp4y_en,
+ SHU_B1_DQ13_RG_TX_ARDQSB_OE_TIE_EN_B1, lp4y_en);
+ SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd0,
+ SHU_CA_CMD0_R_LP4Y_WDN_MODE_CLK, 0);
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq0,
+ SHU_B0_DQ0_R_LP4Y_WDN_MODE_DQS0, 0);
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq0,
+ SHU_B1_DQ0_R_LP4Y_WDN_MODE_DQS1, 0);
+ SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd7,
+ SHU_CA_CMD7_R_LP4Y_SDN_MODE_CLK, 0);
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq7,
+ SHU_B0_DQ7_R_LP4Y_SDN_MODE_DQS0, lp4y_en);
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq7,
+ SHU_B1_DQ7_R_LP4Y_SDN_MODE_DQS1, lp4y_en);
+ SET32_BITFIELDS(&ch[0].phy_ao.ca_cmd7,
+ CA_CMD7_RG_TX_ARCLKB_PULL_DN_LP4Y, 0);
+ SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq7,
+ B0_DQ7_RG_TX_ARDQS0B_PULL_DN_B0_LP4Y, 0);
+ SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq7,
+ B1_DQ7_RG_TX_ARDQS0B_PULL_DN_B1_LP4Y, 0);
+}
diff --git a/src/soc/mediatek/mt8192/emi.c b/src/soc/mediatek/mt8192/emi.c
index b587993..acd605f 100644
--- a/src/soc/mediatek/mt8192/emi.c
+++ b/src/soc/mediatek/mt8192/emi.c
@@ -320,6 +320,27 @@
return ma_type;
}
+u32 get_row_width_from_emi(u32 rank)
+{
+ u32 emi_cona;
+ u32 shift_row, shift_ext;
+ int row_width;
+
+ if (rank == 0) {
+ shift_row = 12;
+ shift_ext = 22;
+ } else if (rank == 1) {
+ shift_row = 14;
+ shift_ext = 23;
+ } else
+ return -1;
+
+ emi_cona = read32(&emi_reg->cona);
+ row_width = ((emi_cona >> shift_row) & 0x3) | ((emi_cona >> shift_ext) & 0x4);
+
+ return (row_width + 13);
+}
+
static void emi_sw_setting(void)
{
setbits32(&emi_mpu->mpu_ctrl_d[1], BIT(4));
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