Tobias Diedrich has uploaded this change for review. ( https://review.coreboot.org/22836
Change subject: intel/dcp847ske: Enable RAM voltage setting ......................................................................
intel/dcp847ske: Enable RAM voltage setting
Use the hooks introduced in https://review.coreboot.org/#/c/22806/ to enable setting the RAM voltage before RAM training.
Change-Id: Ib0e2b4e90b5eda2da14834f4721649fd77ec1025 Signed-off-by: Tobias Diedrich ranma+coreboot@tdiedrich.de --- M src/mainboard/intel/dcp847ske/romstage.c 1 file changed, 18 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/22836/1
diff --git a/src/mainboard/intel/dcp847ske/romstage.c b/src/mainboard/intel/dcp847ske/romstage.c index ad31bba..98bc6dd 100644 --- a/src/mainboard/intel/dcp847ske/romstage.c +++ b/src/mainboard/intel/dcp847ske/romstage.c @@ -16,7 +16,9 @@ * GNU General Public License for more details. */
+#include <console/console.h> #include <stdint.h> +#include <southbridge/intel/common/gpio.h> #include <northbridge/intel/sandybridge/sandybridge.h> #if IS_ENABLED(CONFIG_USE_NATIVE_RAMINIT) #include <northbridge/intel/sandybridge/raminit_native.h> @@ -24,7 +26,22 @@ #include <northbridge/intel/sandybridge/raminit.h> #endif
-#if !IS_ENABLED(CONFIG_USE_NATIVE_RAMINIT) +#if IS_ENABLED(CONFIG_USE_NATIVE_RAMINIT) +void mainboard_supported_dram_voltage(dimm_voltage_t *voltage) +{ + voltage->min_millivolts = 1350; + voltage->max_millivolts = 1500; +} + +void mainboard_set_dram_voltage(const u16 voltage) +{ + if (voltage < 1500) { + // GPIO8 default from gpio.c is LOW (1.5V). + // Set to HIGH to lower ram voltage to 1.35V. + set_gpio(8, 1); + } +} +#else void mainboard_fill_pei_data(struct pei_data *pei_data) { struct pei_data pei_data_template = {