[coreboot-gerrit] [S] Change in coreboot[master]: mb/google/rex: Disable stage cache

[Subrata Banik (Code Review)]

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/71695 )

Change subject: mb/google/rex: Disable stage cache
......................................................................

mb/google/rex: Disable stage cache

This patch disables the stage cache to save boot time.

Note: S3 is not POR for Intel MTL mobile skus.

Boot time is reduced by ~8ms.

Boot time before:
   4:end of romstage                1,391,225 (13,724)
 100:start of postcar               1,403,339 (12,114)

Boot time after:
   4:end of romstage                1,380,262 (5,618)
 100:start of postcar               1,392,323 (12,060)

Change-Id: I9775fc628f345a514894f30435a374e2ffa057c1
Signed-off-by: Subrata Banik 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71695
Tested-by: build bot (Jenkins) 
Reviewed-by: Tarun Tuli 
Reviewed-by: Kapil Porwal 
---
M src/mainboard/google/rex/Kconfig
1 file changed, 29 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Tarun Tuli: Looks good to me, approved
  Kapil Porwal: Looks good to me, approved

diff --git a/src/mainboard/google/rex/Kconfig b/src/mainboard/google/rex/Kconfig
index 897bf9a..a0eeaea 100644
--- a/src/mainboard/google/rex/Kconfig
+++ b/src/mainboard/google/rex/Kconfig
@@ -21,6 +21,7 @@
    select HAVE_ACPI_TABLES
    select I2C_TPM
    select INTEL_LPSS_UART_FOR_CONSOLE
+	select MAINBOARD_DISABLE_STAGE_CACHE
    select MAINBOARD_HAS_TPM2
    select PMC_IPC_ACPI_INTERFACE
    select SOC_INTEL_CSE_LITE_SKU